- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383990 > TDA9874APS (NXP SEMICONDUCTORS) Digital TV sound demodulator/decoder PDF資料下載
參數(shù)資料
| 型號(hào)： | TDA9874APS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 接收器 |
| 英文描述： | Digital TV sound demodulator/decoder |
| 中文描述： | AM/FM, AUDIO DEMODULATOR, PDIP42 |
| 封裝： | 0.600 INCH, SHRINK, PLASTIC, MS-020, SOT-270-1, DIP-42 |
| 文件頁(yè)數(shù)： | 56/68頁(yè) |
| 文件大?。?/td> | 231K |
| 代理商： | TDA9874APS |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
1999 Dec 03
56
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
10.4.7
T
EST
R
EGISTER
2 (TR2)
This register contains, as a binary number, the highest
subaddress used for slave receiver registers.
The first version will have the identification ‘0010 1101’.
Table 88
Test register 2 (subaddress 252)
10.4.8
T
EST
R
EGISTER
1 (TR1)
This register contains, as a binary number, the highest
subaddress used for slave transmitter (status) registers.
The first version will have the identification ‘0000 0111’.
Table 89
Test register 1 (subaddress 253)
10.4.9
D
EVICE
I
DENTIFICATION
C
ODE
(DIC)
There will be several devices in the digital TV sound
processor family, with TDA9874A being the second
member. This byte is used to identify the individual family
members.
The first version will have the identification ‘0001 0001’.
Table 90
Device identification code (subaddress 254)
10.4.10 S
OFTWARE
I
DENTIFICATION
C
ODE
(SIC)
It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g. to
incorporate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.
The first version will have the identification ‘0000 0010’.
Table 91
Software identification code (subaddress 255)
11 I
2
S-BUS DESCRIPTION
The digital audio interface of the TDA9874A consists of a
serial audio output and associated clock signals. It can be
used to supply digital audio signals from received TV
programs to a suitable output device, e.g. a DAC or an
AES/EBU transmitter.
Two serial audio formats are supported at the digital audio
interface, the I
2
S-bus format and a very similar
MSB-aligned format. The difference is illustrated in Fig.8.
In both formats the left audio channel of a stereo sample
pair is output first, and is on the Serial Data line (SDO)
when the Word Select line (WS) is LOW. Data is written on
the trailing edge of SCK and read on the leading edge of
SCK. The most significant bit is sent first.
After power-on reset, the outputs of the digital audio
interface are 3-stated to reduce EMC and allow for
combinations with other ICs. If an output is desired, it has
to be activated by means of an I
2
C-bus command.
When the output is enabled, serial audio data can be taken
frompin SDO.Dependingonthesignalsource,switchand
matrix positions, the output can be either mono, stereo or
dual language.
The Word Select output (WS) is clocked with the audio
sample frequency of 32 kHz. The Serial Clock output
(SCK) is clocked at a frequency of 2.048 MHz. This means
that there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. There are
18 significant bits used on the Serial Data Output (SDO).
A symmetrical system clock output (SYSCLK) is available
from the TDA9874A as a master clock for external digital
audio devices. After Power-on reset, the clock is off. It can
be enabled and the output frequency set via an I
2
C-bus
command. Available output frequencies are
8.192, 12.288, 16.384 and 24.576 MHz.
7
6
5
4
3
2
1
0
B7
B6
B5
B4
B3
B2
B1
B0
7
6
5
4
3
2
1
0
B7
B6
B5
B4
B3
B2
B1
B0
7
6
5
4
3
2
1
0
B7
B6
B5
B4
B3
B2
B1
B0
7
6
5
4
3
2
1
0
B7
B6
B5
B4
B3
B2
B1
B0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDCS6440G | SONET/SDH 40 Gbits/s Cross Connect( SONET/SDH 40G位/秒交叉連接器件) |
| TDK5100F | 434 MHz ASK/FSK Transmitter in 10-pin Package |
| TDK5100 | ASK/FSK Transmitter 868/433 MHz |
| TE28F004S3-150 | BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| TE28F008S3-150 | BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9874H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV sound demodulator/decoder |
| TDA9875 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital TV Sound Processor DTVSP |
| TDA9875AH/V2,557 | 功能描述:IC SOUND PROC DGTL TV 64QFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。