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參數(shù)資料
| 型號： | TH50VSF2581AASB |
| 廠商： | Toshiba Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:7; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Square Flange Receptacle; Body Style:Straight |
| 中文描述： | SRAM和閃存混合多芯片封裝 |
| 文件頁數(shù)： | 44/50頁 |
| 文件大小： | 546K |
| 代理商： | TH50VSF2581AASB |
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TH50VSF2580/2581AASB
2001-10-26 44/50
SRAM DATA RETENTION CHARACTERISTICS
(Ta
=
-40
°
~85
°
C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
V
DH
Data Retention Supply Voltage for SRAM
1.5
3.6
V
V
DH
=
3.0 V
5
I
CCS4
SRAM Standby Current
V
DH
=
3.6 V
7
μ
A
t
CDR
Chip-Deselect-to-Data-Retention-Mode Time
0
ns
t
r
Recovery Time
t
RC
(1)
ns
(1) Read cycle time
-CONTROLLED DATA RETENTION MODE (see Note 1)
CE2S-CONTROLLED DATA RETENTION MODE (see Note 3)
Notes:
(1)
In
CE2S
≤
0.2 V or CE2S
≥
V
CCs
0.2 V.
S
1
CE
-Controlled Data Retention Mode the device enters Minimum Standby Current Mode when
(2)
When
V
CCs
from 3.6 V to 2.4 V.
S
1
CE
is at V
IH
(2.2 V), the SRAM standby current is the same as I
CCS3
during the transition of
(3)
In CE2S-Controlled Data Retention Mode the device enters Minimum Standby Current Mode when
CE2S
≤
0.2 V.
V
CCs
2.7 V
GND
S
1
CE
V
IH
Data Retention Mode
t
r
(See Note 2)
(See Note 2)
t
CDR
V
CCs
V
CCs
0.2 V
V
CCs
2.7 V
GND
V
IL
Data Retention Mode
t
CDR
V
CCs
0.2 V
V
IH
CE2S
t
r
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| TH50VSF3582AASB | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS |
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