參數(shù)資料
型號(hào)： THS770012IRGET
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC24
封裝： GREEN, PLASTIC, VQFN-24
文件頁(yè)數(shù)： 16/35頁(yè)
文件大?。?/td> 1305K
代理商： THS770012IRGET
0
60
Frequency - MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
dBFS
25
30 35
5
15
20
55
40
45 50
10
65
SLOS669B
– FEBRUARY 2010 – REVISED MAY 2011
APPLICATION INFORMATION
THS770012 DRIVING ADS5493
To illustrate the performance of the THS770012 as an ADC driver, the device is tested with the ADS5493. The
ADS5493 is a 16-bit, 130MSPS ADC with LVDS-compatible digital outputs on four data pairs. The device has an
analog input buffer to isolate the internal switching of the sampling stage from the inputs. Designed for high
SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large
input-frequency range. Key information points to consider when interfacing to an amplifier are:
Input buffer with constant load vs frequency
3.15V analog input common mode
Full-scale differential input programmable from 1.5VPP to 2.5VPP
2k
Ω differential input impedance with internal common-mode bias
4.6pF to 5.6pF for each analog input to ground (depending on PCB layout)
SNR = 75.2dBFS (typ) at fIN = 100MHz
SFDR = 100dBc (typ) at fIN = 100MHz
HD2 = 100dBc (typ) at fIN = 100MHz
HD3 = 100dBc (typ) at fIN = 100MHz
For testing purposes, a 30MHz, second-order Butterworth bandpass filter with center frequency at 100MHz is
designed. The design target for the source impedance is 40
Ω differential, and for load impedance is 400Ω
differential. Therefore, approximately 1dB insertion loss is expected in the pass-band, requiring the amplifier
output amplitude to be 2.5VPP to drive the ADC to –1dBFS.
The output noise voltage specification for the THS770012 is 6 nV/
√Hz. With 2.5VPP amplifier output voltage
swing and 30MHz bandwidth, the expected SNR from the amplifier + antialias filter is 88.5dBc. When added in
combination with the ADS5493, the expected total SNR is 75.2dBFS for the typical case.
Figure 42 shows the resulting FFT plot when driving the ADC to
–1dBFS with a single-tone 95MHz sine wave,
and sampling at 130MSPS. Test results show 100dBc SFDR from the forth-order harmonic and 74.4 dBFS SNR;
analysis of the plot is shown in Table 4 versus typical ADC specifications. The test results from circuit board to
circuit board shows over 10dB of variation in the second order harmonic due to component tolerance. Using
lower 1% tolerance components or adding a balun between the filter and ADC inputs resulted in less variation
and the typical expected results should be better than 95dBc SFDR and 74dB SNR.
Figure 42. FFT Plot of THS770012 + 30MHz BPF + ADS5493 with 95MHz Single-Tone Input Sampling at
130MSPS
Table 4. Analysis of FFT for THS770012 + BPF + ADS5493 at 95MHz vs Typical ADC Specifications
CONFIGURATION
ADC INPUT
SNR
HD2
HD3
THS770012 + BPF + ADS5493
–1dBFS
74.4dBFS
–101dBc
ADS5493 Only (typ)
–1dBFS
75.2dBFS
–100dBc
Copyright
2010–2011, Texas Instruments Incorporated
23
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