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參數(shù)資料
| 型號： | THS770012IRGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數(shù)： | 31/35頁 |
| 文件大?。?/td> | 1305K |
| 代理商： | THS770012IRGET |
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SLOS669B
– FEBRUARY 2010 – REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400 differential, G = +12dB, differential input
and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as
discussed in Test Circuits section.
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
OUTPUT COMMON-MODE VOLTAGE CONTROL
VOCM small-signal bandwidth
VOUT_CM = 200mVPP
300
MHz
C
VOCM slew rate
VOUT_CM = 500mV step
150
V/
s
C
VOCM voltage range
Supplied by external source(2)
2.25
2.5
2.75
V
C
VOCM gain
VOCM = 2.5V
0.98
1
1.02
V/V
A
Output common-mode offset
VOCM = 2.5V
–30
±12
30
mV
A
from VOCM input
VOCM input bias current
2.25V
≤ VOCM ≤ 2.75V
–400
±30
400
A
POWER SUPPLY
Specified operating voltage
4.75
5
5.25
V
C
TA = +25°C
85
100
115
mA
A
Quiescent current
TA = –40°C to +85°C
80
125
mA
B
TA = +25°C, VS+ = 5V ±0.25V
60
90
dB
A
Power-supply rejection ratio
TA = –40°C to +85°C, VS+ = 5V ±0.5V
59
dB
B
POWER-DOWN
Enable voltage threshold
Device powers on below 0.5V
0.5
V
A
Disable voltage threshold
Device powers down above 2.0V
2
V
A
Power-down quiescent current
0.8
3
mA
A
Input bias current
80
100
A
Turn-on time delay
Time to VOUT = 90% of final value
10
s
C
Turn-off time delay
Time to VOUT = 10% of original value
0.15
s
C
THERMAL CHARACTERISTICS
Specified operating range
–40
+85
°C
C
Thermal resistance,
θJC
(3)
Junction to case (bottom)
8.9
°C/W
C
Thermal resistance,
θJA
(3)
Junction to ambient
44.1
°C/W
C
(2)
Limits set by best harmonic distortion with VOUT = 3VPP. VOCM voltage range can be extended if lower output swing is used or distortion
degradation is allowed, and increased bias current into pin is acceptable. For more information, see Figure 18 and Figure 34.
(3)
Tested using JEDEC High-K test PCB. Thermal management of the final printed circuit board (PCB) should keep the junction
temperature below +125
°C for long term reliability.
Copyright
2010–2011, Texas Instruments Incorporated
5
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