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參數(shù)資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 30/63頁 |
| 文件大?。?/td> | 320K |
| 代理商： | THS8083APZPG4 |
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41
4 Register Definition
4.1
I2C Protocol
The THS8083A is a slave I2C device that supports both write and read. As shown in Table 31, I2C Register Map,
there are some status control registers that can only be read.
The device can support FAST I2C mode (SCL up to 400 kHz) when the DTO clock is running at over 25 MHz; at lower
DTO frequencies, only NORMAL I2C mode (SCL up to 100 kHz) is supported.
To discriminate between write and read operations, the device is addressed at separate device addresses. There is
an automatic internal subaddress increment counter to efficiently write/read multiple bytes in the register map during
one write/read operation. Furthermore, bit 1 of the I2C device address is dependent upon the I2CA pin setting, as
follows:
If address selecting pin I2CA = 0, then
Write address is 40 hex (01000000)
Read address is 41 hex (01000001)
If address selecting pin I2CA = 1, then
Write address is 42 hex (01000010)
Read address is 43 hex (01000011)
4.1.1
Write Format
S
Slave address(w)
A
Subaddress
A
Data0
A
……
Data(N1)
A
P
S
Start condition
Slave address(w)
0100000 (0x40) if I2CA=0 / 01000010 (0x42) if I2CA=1
A
Acknowledge. It is generated by THS8083A.
Subaddress
Subaddress of first register to write, length: 1 byte
Data0
First byte of data
Data(N1)
Nth byte of data
P
Stop condition
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