參數(shù)資料
型號(hào): TISP61089HDM
廠商: Bourns Inc.
英文描述: DUAL FORWARD-CONDUCTING P-GATE THYRISTOR PROGRAMMABLE OVERVOLTAGE PROTECTOR
中文描述: 雙遠(yuǎn)期導(dǎo)電的P -門晶閘管可編程過(guò)壓保護(hù)
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 151K
代理商: TISP61089HDM
MAY 2004 – REVISED FEBRUARY 2005
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Absolute Maximum Ratings, TA = 25
°
C (Unless Otherwise Noted)
TISP61089HDM Overvoltage Protector
Electrical Characteristics, TA = 25
°
C (Unless Otherwise Noted)
Parameter
Description (Continued)
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC
negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state
condition. As the overvoltage subsides the high holding current of TISP61089HDM SCR prevents d.c. latchup.
The TISP61089HDM is designed to be used with a pair of Bourns
B1250T fuses for overcurrent protection. Level 2 power fault compliance
requires the series overcurrent element to become open-circuit or high impedance. For equipment compliant to ITU-T recommendations K.20,
K.21 or K.45 only, the series resistor value is set by the coordination requirements. For coordination with a 400 V limit GDT, a minimum series
resistor value of 6.5
is recommended.
Rating
Symbol
V
DRM
V
GKRM
Value
-170
-167
Unit
V
V
Repetitive peak off-state voltage, V
GK
= 0
Repetitive peak gate-cathode voltage, V
KA
= 0
Non-repetitive peak impulse current (see Notes 1, 2 and 3)
10/1000
μ
s (Telcordia GR-1089-CORE, Issue 3)
5/310
μ
s (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700
μ
s)
10/360
μ
s (Telcordia GR-1089-CORE, Issue 3)
1.2/50
μ
s voltage waveshape (Telcordia GR-1089-CORE, Issue 3), including 3
non-inductive resistor
2/10
μ
s (Telcordia GR-1089-CORE, Issue 3)
Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 4)
0.5 s
1 s
2 s
5 s
30 s
900 s
Junction temperature
Storage temperature range
I
PPSM
100
150
100
500
500
A
I
TSM
7.7
6.1
4.8
3.7
2.8
2.6
A
T
J
T
stg
-40 to +150
-65 to +150
°
C
°
C
NOTES: 1. Initially the device must be in thermal equilibrium with T
J
= 25
°
C. The surge may be repeated after the device returns to its initial
conditions.
2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally both
terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the
rated current value of an individual terminal pair). Ratings are obtained by using the gate circuitry as shown in Fig. 3.
3. Rated currents only apply if pins 1 & 8 (Tip) are connected together, pins 4 & 5 (Ring) are connected together and pins 6 & 7
(Anode) are connected together.
4. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm
printed wiring track widths.
Test Conditions
Min Typ Max Unit
I
D
Off-state current
V
D
= V
DRM
, V
GK
= 0
T
A
= 25
°
C
T
A
= 85
°
C
-5
-50
12
12
20
3
6
7
10
μ
A
V
GK(BO)
Gate-cathode impulse breakover voltage
10/1000
μ
s, I
TM
= 100 A, V
GG
= -100 V
5/310
μ
s, I
TM
= 150 A, V
GG
= -100 V
2/10
μ
s, I
TM
= 200 A, V
GG
= -100 V (see Note 5)
I
F
= 5 A, t
W
= 200
μ
s
10/1000
μ
s, I
F
= 100 A, V
GG
= -100 V
5/310
μ
s, I
F
= 150 A, V
GG
= -100 V
2/10
μ
s, I
F
= 200 A, V
GG
= -100 V (see Note 5)
V
V
F
Forward voltage
V
V
FRM
Peak forward recovery voltage
V
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