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參數(shù)資料
| 型號： | TLC32040MFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ANALOG INTERFACE CIRCUIT |
| 中文描述： | 模擬接口電路 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 202K |
| 代理商： | TLC32040MFK |
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TLC32040M
ANALOG INTERFACE CIRCUIT
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4–19
correction results
Table 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates.
Table 4. Optimum P Values
f (Hz)
ERROR (dB)
fs = 8000 Hz
p1 = –0.14813
p2 = 0.9888
–0.099
–0.089
–0.054
–0.002
0.041
0.079
0.100
0.091
–0.043
–0.102
ERROR (dB)
fs = 9600 Hz
p1 = –0.1307
p2 = 0.9951
–0.043
–0.043
0
0
0
0.043
0.043
0.043
0
–0.043
300
600
900
1200
1500
1800
2100
2400
2700
3000
SMJ320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1Y + k2U
where k1 equals p1 (from the preceding page), k2 equals (1 – p1)p2 (from the preceding page), Y is the filter
state, and U is the next I/O sample. The coefficients k1 and k2 must be represented as 16-bit integers. The
SACH instruction (with the proper shift) will yield the correct result. With the assumption that the SMJ320
processor page pointer and memory configuration are properly initialized, the equation can be executed in
seven instructions or seven cycles with the following program:
ZAC
LT K2
MPY U
LTA K1
MPY Y
APAC
SACH (dma), (shift)
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