參數(shù)資料
型號(hào): TLV2553IDWRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, SOIC-20
文件頁(yè)數(shù): 10/28頁(yè)
文件大?。?/td> 414K
代理商: TLV2553IDWRQ1
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
1
2
3
5
4
6
1
MSB1 MSB2 MSB3 MSB4 MSB5
LSB+1
LSB
HiZ State
2
3
D6
D5
D4
D3
D2
D1
D0
D6
D5
D7
8
7
D7
MSB
MSB2
MSB1
4
5
6
7
D4
D3
MSB4
MSB3
D2
D1
MSB6
MSB5
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Initialize
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
MSB
1
2
3
5
4
6
1
MSB1 MSB2 MSB3 MSB4 MSB5
LSB+1
LSB
2
3
D6
D5
8
7
D7
Low Level
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB2
MSB1
4
5
6
7
D4
D3
MSB4
MSB3
D2
D1
MSB6
MSB5
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Parameter Measurement Information (continued)
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
18
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
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