參數(shù)資料
型號： TLV2553IDWRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： GREEN, PLASTIC, SOIC-20
文件頁數(shù)： 25/28頁
文件大?。?/td> 414K
代理商： TLV2553IDWRQ1
EXTERNAL REFERENCE SPECIFICATIONS
(1)
OPERATING CHARACTERISTICS
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
PARAMETER
TEST CONDITIONS
MIN TYP(2)
MAX
UNIT
VCC = 4.5 V to 5.5 V
–0.1
0
0.1
VREF–
Reference input voltage, REF–
V
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
VCC = 4.5 V to 5.5 V
2
VCC
VREF+
Reference input voltage, REF+
V
VCC = 2.7 V to 3.6 V
2
VCC
VCC = 4.5 V to 5.5 V
1.9
VCC
External reference input voltage difference
V
(REF+ – REF–)
VCC = 2.7 V to 3.6 V
1.9
VCC
VCC = 4.5 V to 5.5 V
0.94
IREF
External reference supply current
CS = 0 V
mA
VCC = 2.7 V to 3.6 V
0.62
Static
1
M
VCC = 5 V
During sampling/conversion
6
9
k
ZREF
Reference input impedance
Static
1
M
VCC = 2.7 V
During sampling/conversion
6
9
k
(1)
Add a 0.1-
F capacitor between REF+ and REF– pins when external reference is used.
(2)
All typical values are at VCC = 5 V, TA = 25°C.
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
INL
Integral linearity error(2)
–1
1
LSB
DNL
Differential linearity error
–1
1
LSB
EO
Offset error(3)
See (4)
–2
2
mV
EG
Gain error(3)
See (4)
–3
3
mV
ET
Total unadjusted error(5)
±1.5
LSB
Address data input = 1011
2048
Self-test output code(6) (see Table 2)
Address data input = 1100
0
Address data input = 1101
4095
(1)
All typical values are at VCC = 5 V, TA = 25°C.
(2)
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3)
Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
(4)
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
(5)
Total unadjusted error comprises linearity, zero-scale errors, and full-scale errors.
(6)
Both the input address and the output codes are expressed in positive logic.
6
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
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