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| 型號： | TLV2553IDWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 414K |
| 代理商： | TLV2553IDWRQ1 |
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TIMING CHARACTERISTICS
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
over recommended operating free-air temperature range,
VREF+ = 5 V, I/O CLOCK frequency = 15 MHz, VCC = 5 V, Load = 25 pF (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw1
Pulse duration I/O CLOCK high or low
26.7
100000
ns
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
12
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
0
ns
tsu2
25
ns
th2
Hold time CS pulse duration high time (see Figure 27)
100
ns
th3
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
0
ns
Load = 25 pF
28
Delay time CS falling edge to DATA OUT valid (MSB or LSB)
td1
ns
(see Figure 25)
Load = 10 pF
20
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
10
ns
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
2
20
ns
td4
Delay time last I/O CLOCK falling edge to EOC falling edge
55
ns
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
s
tt1
1
s
tt2
Transition time DATA OUT (see Figure 28)
5
ns
tt3
2.4
ns
tt4
Transition time DATA IN, CS
10
s
tcycle
Total cycle time (sample, conversion and delays)(1)
(2)
s
Source impedance = 25
600
Source impedance = 100
650
Channel acquisition time (sample) at 1 k
(1)
tsample
ns
Source impedance = 500
700
Source impedance = 1 k
1000
(1)
I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending
on I/O format selected
(2)
tconvert(max) + I/O CLOCK period (8/12/16 CLKs)
Copyright 2009, Texas Instruments Incorporated
7
Product Folder Link(s): TLV2553-Q1
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