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參數(shù)資料
| 型號(hào)： | TLV320AIC10IGQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | MICRO, PLASTIC, BGA-80 |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 454K |
| 代理商： | TLV320AIC10IGQER |
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3–3
3.2.1
Register Programming
All register programming occurs during secondary communication through DIN or ALTI, and data are latched and
valid on the falling edge of the SCLK during the frame-sync signal. If the default value of a particular register is desired,
that register does not need to be addressed during the secondary communication interval. The NOOP command
(DS15-DS8 all set to 0) addresses the pseudo-register (register 0), and no register programming takes place during
the communication.
In addition, each register can be read back through DOUT during secondary communications by setting the read bit
(D12) to 1. When a register is in the read mode, no data can be written to the register during this cycle. A subsequent
secondary communication is required to return this register to the write mode.
For example, if the contents of control register 1 of device 3 are desired to be read out from DOUT, the following
procedure must be performed through DIN:
Request secondary communication by setting either D0 = 1(software request), or FC = high (hardware
request) during the primary communication interval.
During the secondary communication interval (FS), send data in through DIN using the following format:
Device Address
RW
Register Address
X
Register Content
0
1
0
1
x
DS15
DS0
Then, during the same frame, the following data is read from DOUT; the last 8 bits of DOUT contains
register 1 data.
Device Address
RW
Register Address
X
Register Content
0
1
x
d
DS15
DS0
Figure 3–3 is the timing diagram of this procedure.
DOUT
PS
DIN
Register 1 Read
FS
Low 8 Bit (D0 – D7) Is
the Content of Register
1
Figure 3–3. Device 3/Register 1 Read Operation Timing Diagram
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