參數(shù)資料
型號: TLV320AIC10IGQER
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: MICRO, PLASTIC, BGA-80
文件頁數(shù): 4/57頁
文件大?。?/td> 454K
代理商: TLV320AIC10IGQER
1–6
1.5
Terminal Functions
TERMINALS
I/O
NAME
NO.
I/O
DESCRIPTION
NAME
PFB
GQE
I/O
DESCRIPTION
ALTIN
26
G9
I
Serial input in the event monitor mode. Tie this pin to low if not used.
AURXCP
3
C1
I
Receiver-path/GP amplifier noninverting input. It needs to be connected to AVSS if not used.
AURXM
2
C2
I
Receiver-path amplifier A1 inverting input, or inverting input to auxiliary analog input. It needs to be
connected to AVSS if not used. Can also be used for general-purpose amplification.
AURXFP
1
B1
I
Receiver-path amplifier A1 feedback, or noninverting input to auxiliary analog input. It needs to be
connected to AVSS if not used. Can also be used for general-purpose amplification.
AVDD1
45
B4
I
Analog power supply
AVDD2
34
D8
I
Analog power supply
AVSS
33, 40,
42, 46
A3, B3,
B5, B6,
D9
I
Analog ground
DCSI
25
G8
I
Direct configuration serial input for directly programming of internal control registers. Tie this pin to
high if not used.
DIN
17
J4
I
Data input. DIN receives the DAC input data and register data from the external digital signal
processor (DSP), and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK
when FS is low. DIN is at high impedance when FS is not activated.
DOUT
16
H4
O
Data output. DOUT transmits the ADC output bits and registers data, and is synchronized to SCLK
and FS. Data is sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when
FS is not activated.
DTXIM
7
E1
I
Transmitter-path amplifier A3 analog inverting input. Can also be used for general-purpose
amplification.
DTXIP
6
E2
I
Transmitter-path amplifier A4 analog noninverting input. Can also be used for general-purpose
amplification.
DTXOM
5
D1
O
Transmitter path amplifier A4 feedback for negative output. Can also be used for general-purpose
amplification.
DTXOP
4
D2
O
Transmitter path amplifier A3 feedback for positive output. Can also be used for negative output.
DVDD1
15
J3
I
Digital power supply
DVDD2
30
E9
I
Digital power supply
DVSS
14, 29
E8, H3
I
Digital ground
FC
24
H7
I
Hardware request for secondary communication. Tie this pin to low if not used.
FILT
38
B7
O
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 2.5 V. The
optimal capacitor value is 0.1
F (ceramic). This voltage node should be loaded only with a
high-impedance dc load.
FLAG
23
J7
O
Controlled by bit D4 of control register 3. If D4=0 (default), the FLAG pin outputs the communication
flag that goes low/high to indicate primary-communication/secondary-communication interval,
respectively. If D4=1, the FLAG pin outputs the value of D3.
FS
22
H6
I/O
Frame sync. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data
bits. In master mode, FS is internally generated and is low during data transmission to DIN and from
DOUT. In slave mode, FS is externally generated.
FSD
21
J6
O
Frame-sync delayed output. The FSD output synchronizes a slave device to the frame sync of the
master device. FSD is applied to the slave FS input and has the same duration as the master FS
signal. Requires a pullup resistor if not used.
INM
48
B2
I
Inverting input to analog modulator. INM requires an external R-C antialias filter with low output
impedance if the internal antialias filter is bypassed.
INP
47
A2
I
Noninverting input to analog modulator. INP requires an external R-C antialias filter with low output
impedance if the internal antialias filter is bypassed.
M0
10
G1
I
Combine with M1 to select serial interface mode (frame-sync mode)
M1
11
G2
I
Combine with M0 to select serial interface mode (frame-sync mode)
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