SLAS647 – DECEMBER 2009
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time. This feature is enabled by register programming of the various pin selections.
Table 5-43 shows the
primary and secondary audio interface selection and registers.
Table 5-44 shows the selection criteria for
generating ADC_WCLK.
Figure 5-50 is a high-level diagram showing the general signal flow and
multiplexing for primary and secondary audio interfaces. For detailed information, see
Table 5-43,
Table 5-43. Primary and Secondary Audio Interface Selection
Desired Pin
Possible
Page 0 Registers
Comment
Function
Pins
R27/D2 = 1
Primary WCLK is output from codec
Primary WCLK
WCLK
(OUT)
R33/D5–D4
Select source of primary WCLK (DAC_fs, ADC_fs, or secondary WCLK)
Primary WCLK (IN)
WCLK
R27/D2 = 0
Primary WCLK is input to codec
R27/D3 = 1
Primary BCLK is output from codec
Primary BCLK
BCLK
(OUT)
R33/D7
Select source of primary WCLK (internal BCLK or secondary BCLK)
Primary BCLK (IN)
BCLK
R27/D3 = 0
Primary BCLK is input to codec
Primary DIN (IN)
DIN
R32/D0
Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN)
R53/D3–D1 = 001
DOUT = primary DOUT for codec interface
Primary DOUT
DOUT
(OUT)
R33/D1
Select source for DOUT (0 = DOUT from interface block; 1 = secondary DIN)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
GPIO1
R51/D5–D2 = 1001
GPIO1 = secondary WCLK output
R33/D3–D2
Select source of secondary WCLK (DAC_fS, ADC_fS, or primary WCLK)
Secondary WCLK
(OUT)
R31/D4–D2 = 011
Secondary WCLK obtained from DOUT pin
DOUT
R53/D3–D1 = 111
DOUT = secondary WCLK output
R33/D3–D2
Select source of secondary WCLK (DAC_fS, ADC_fS, or primary WCLK)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
Secondary WCLK
GPIO1
(IN)
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R31/D7–D5 = 000
Secondary BCLK obtained from GPIO1 pin
GPIO1
R51/D5–D2 = 1000
GPIO1 = secondary BCLK output
R33/D6
Select source of secondary BCLK (primary BCLK or internal BCLK)
Secondary BCLK
(OUT)
R31/D7–D5 = 011
Secondary BCLK obtained from DOUT pin
DOUT
R53/D3–D1 = 110
DOUT = secondary BCLK output
R33/D6
Select source of secondary BCLK (primary BCLK or internal BCLK)
R31/D7–D5 = 000
Secondary BCLK obtained from GPIO1 pin
Secondary BCLK
GPIO1
(IN)
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R31/D1–D0 = 00
Secondary DIN obtained from GPIO1 pin
Secondary DIN (IN)
GPIO1
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R51/D5–D2 = 1011
GPIO1 = secondary DOUT
Secondary DOUT
GPIO1
Select source for secondary DOUT (0 = primary DIN; 1 = DOUT from
(OUT)
R33/D0
interface block)
Table 5-44. Generation of ADC_WCLK
ADC_WCLK
Possible
Page 0 Registers
Comment
Direction
Pins
R32/D7–D5 = 000
ADC_WCLK obtained from GPIO1 pin
OUTPUT
GPIO1
R51/D5–D2 = 0111
GPIO1 = ADC_WCLK
R32/D1
Select source of internal ADC_WCLK (0 = DAC_WCLK; 1 = ADC_WCLK)
R32/D7–D5 = 000
ADC_WCLK obtained from GPIO1 pin
INPUT
GPIO1
R51/D5–D2 = 0001
GPIO1 enabled as secondary input
R32/D1
Select source of internal ADC_WCLK (0 = DAC_WCLK; 1 = ADC_WCLK)
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