參數(shù)資料
型號: TLV320AIC3110IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 119/126頁
文件大?。?/td> 1528K
代理商: TLV320AIC3110IRHBR
SLAS647 – DECEMBER 2009
www.ti.com
Page 0 / Register 61 (0x3D): ADC Processing Blocks Selection
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
Reserved. Write only default values.
D4–D0
R/W
0 0100
0 0000: Reserved. Write only reset value.
0 0001–0 0011: Reserved
0 0100: ADC signal-processing block PRB_R4
0 0101: ADC signal-processing block PRB_R5
0 0110: ADC signal-processing block PRB_R6
0 0111–01001: Reserved
0 1010: ADC signal-processing block PRB_R10
0 1011: ADC signal-processing block PRB_R11
0 1100: ADC signal-processing Block PRB_R12
0 1101–0 1111: Reserved
1 0000: ADC signal-processing block PRB_R16
1 0001: ADC signal-processing block PRB_R17
1 0010: ADC signal-processing block PRB_R18
1 0011–1 1111: Reserved. Do not write these sequences to these bits.
Page 0 / Register 62 (0x3E): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
0000 0000
Reserved. write only reset values.
Page 0 / Register 63 (0x3F): DAC Data-Path Setup
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Left-channel DAC is powered down.
1: Left-channel DAC is powered up.
D6
R/W
0
0: Right-channel DAC is powered down.
1: Right-channel DAC is powered up.
D5–D4
R/W
01
00: Left-channel DAC data path = off
01: Left-channel DAC data path = left data
10: Left-channel DAC data path = right data
11: Left-channel DAC data path = left-channel and right-channel data [(L + R)/2]
D3–D2
R/W
01
00: Right-channel DAC data path = off
01: Right-channel DAC data path = right data
10: Right-channel DAC data path = left data
11: Right-channel DAC data path = left-channel and right-channel data [(L + R)/2]
D1–D0
R/W
00
00: DAC channel volume control soft-stepping is enabled for one step per sample period.
01: DAC channel volume control soft-stepping is enabled for one step per two sample periods.
10: DAC channel volume control soft-stepping is disabled.
11: Reserved. Do not write this sequence to these bits.
Page 0 / Register 64 (0x40): DAC VOLUME CONTROL
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved. Write only zeros to these bits.
D3
R/W
1
0: Left-channel DAC not muted
1: Left-channel DAC muted
D2
R/W
1
0: Right-channel DAC not muted
1: Right-channel DAC muted
D1–D0
R/W
00
00: Left and right channels have independent volume control.
01: Left-channel volume control Is the programmed value of right-channel volume control.
10: Right-channel volume control is the programmed value of left-channel volume control.
11: Same as 00
92
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3110
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