BCLK
WCLK
DIN/DOUT
n-1 n-2
1
0
n-1 n-2
1
0
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
1/fs
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SLAS647 – DECEMBER 2009
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see
Figure 5-36). The number of bit-clock pulses in a frame may need adjustment
to accommodate various wordlengths as well as to support the case when multiple TLV320AIC3110s may
share the same audio bus.
The TLV320AIC3110 also includes a feature to offset the position of start of data transfer with respect to
the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in
page 0 / register 28.
The TLV320AIC3110 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
The TLV320AIC3110 further includes programmability (page 0 / register 27, D0) to place the DOUT line in
the high-impedance state during all bit clocks when valid data is not being sent. By combining this
capability with the ability to program at what bit clock in a frame the audio data begins, time-division
multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data
bus. When the audio serial data bus is powered down while configured in master mode, the pins
associated with the interface are put into a high-impedance output state.
By default, when the word clocks and bit clocks are generated by the TLV320AIC3110, these clocks are
active only when the codecs (ADC, DAC or both) are powered up within the device. This is done to save
power. However, it also supports a feature whereby both the word clocks and bit-clocks can be active
even when the codec in the device is powered down. This is useful when using the TDM mode with
multiple codecs on the same bus, or when word clocks or bit clocks are used in the system as
general-purpose clocks.
5.7.1.1
Right-Justified Mode
The audio interface of the TLV320AIC3110 can be put into right-justified mode by programming page 0 /
register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge
of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid
on the rising edge of the bit clock preceding the rising edge of the word clock.
Figure 5-39. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
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