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參數(shù)資料
型號: TLV320AIC31IRHBR
廠商: Texas Instruments
文件頁數(shù): 20/84頁
文件大?。?/td> 0K
描述: IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝: 3,000
類型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 100
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 100
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
配用: 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
AUTOMATIC GAIN CONTROL (AGC)
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
condition, and upon power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag
is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control
can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must
be applied to the part after the ADC power down register is written to ensure the soft-stepping to mute has
completed. When the ADC powerdown flag is no longer set, the audio master clock can be shut down.
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several
programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum
PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses
the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the
nominal amplitude of the output signal.
Note that completely independent AGC circuitry is included with each ADC channel with entirely independent
control over the algorithm from one channel to the next. This is attractive in cases where two microphones are
used in a system, but may have different placement in the end equipment and require different dynamic
performance for optimal system operation.
Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC31 allows programming of eight different target gains, which can be programmed from –5.5 dB to
–24 dB relative to a full-scale signal. Since the device reacts to the signal absolute average and not to peak
levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of
loud sounds.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 8 ms to 20 ms.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 100 ms to 500 ms.
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it
as a silence, and thus reduces the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold flag. The
gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This ensures
that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm is
programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This
operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling
between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is
set, the status of gain applied by the AGC and the saturation flag should be ignored.
Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to +59.5 dB in steps of 0.5 dB.
Copyright 2006–2008, Texas Instruments Incorporated
27
Product Folder Link(s): TLV320AIC31
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