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www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 23:
Reserved Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
0111100
Reserved. Do not write to this register.
0
Page 0 / Register 24:
IN1L to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
IN1L Single-Ended vs Fully-Differential Control If IN1L is selected to both left and right ADC
channels, both connections must use the same configuration (single-ended or fully-differential
mode).
0: IN1L is configured in single-ended mode
1: IN1L is configured in fully-differential mode
D6–D3
R/W
1111
IN1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects IN1L to the right ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: IN1L is not connected to the right ADC PGA
D2–D0
R
000
Reserved. Write only 0s to these register bits.
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
D5–D3
R
000
Reserved. Write only 0s to these register bits.
D2–D0
R
XXX
Reserved. Write only 0s to these register bits.
Copyright 2006–2008, Texas Instruments Incorporated
47