SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ..................................................." />
參數(shù)資料
型號(hào)： TLV320AIC31IRHBR
廠(chǎng)商： Texas Instruments
文件頁(yè)數(shù)： 35/84頁(yè)
文件大小： 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 3,000
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Page 0 / Register 4:
PLL Programming Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
000001
PLL J Value
000000: Reserved, do not write this sequence
000001: J = 1
000010: J = 2
000011: J = 3
…
111110: J = 62
111111: J = 63
D1–D0
R/W
00
Reserved; write only '0' to these bits
Page 0 / Register 5:
PLL Programming Register C(1)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00000000
PLL D value. Eight most significant bits of a 14-bit unsigned integer valid values for D are from 0
to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written
into these registers that would result in a D value outside the valid range.
(1)
Note that whenever the D value is changed, Register 5 should be written, immediately followed by Register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
PLL Programming Register D
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
000000
PLL D value. Six least significant bits of a 14-bit unsigned integer valid values for D are from 0 to
9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written
into these registers that would result in a D value outside the valid range.
D1-D0
R
00
Reserved; write only '0' to these bits.
Page 0 / Register 7:
Codec Datapath Setup Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
FSref setting
This register setting controls timers related to the AGC time constants.
0: FSref = 48 kHz
1: FSref = 44.1 kHz
D6
R/W
0
ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
Note: ADC Dual Rate Mode must match DAC Dual Rate Mode
D5
R/W
0
DAC Dual Rate Control
0: DAC dual rate mode is disabled
1: DAC dual rate mode is enabled
D4–D3
R/W
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1
R/W
00
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0
R/W
0
Reserved. Only write '0' to this register.
40
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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