SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ..................................................." />
參數(shù)資料
型號： TLV320AIC31IRHBR
廠商： Texas Instruments
文件頁數(shù)： 56/84頁
文件大?。?/td> 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At +25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, FS = 48 kHz, 16-bit audio data (unless otherwise noted).
TLV320AIC31
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO DAC
Differential Line Output, load = 10 k
, 50 pF
0-dB gain to line outputs. DAC output
1.414
VRMS
Full-scale differential output
common-mode setting = 1.35 V, output level control
voltage
4.0
VPP
gain = 0 dB
Signal-to-noise ratio,
FS = 48 kHz, 0-dB gain to line outputs, zero signal
90
100
dB
A-weighted(3)
applied, referenced to full-scale input level
FS = 48 kHz, 0-dB gain to line outputs,
Dynamic range, A-weighted
100
dB
1 kHz –60 dB signal applied
Total harmonic distortion
FS = 48 kHz, 1 kHz 0-dB input signal applied
–93
–75
dB
Power-supply rejection ratio
234 Hz, 100 mVPP on AVDD, DRVDD1/2
81
dB
DAC channel separation (left to
1 kHz, 0 dB
–100
dB
right)
DAC interchannel gain mismatch
1-kHz input, 0-dB gain
0.1
dB
DAC Gain Error
1-kHz input, 0-dB gain
–0.26
dB
DAC DIGITAL INTERPOLATION FILTER, FS = 48 kHz
Passband
High-pass filter disabled
0.45 × FS
Hz
Passband ripple
High-pass filter disabled
±0.06
dB
Transition band
0.45 × FS
0.55 × FS
Hz
Stop band
0.55 × FS
7.5 × FS
Hz
Stop band attenuation
65
dB
Group delay
21/FS
Sec
STEREO HEADPHONE DRIVER
AC-Coupled Output Configuration(3)
0-dB gain to high-power outputs.
0-dB full-scale output voltage
0.707
VRMS
Output common-mode voltage setting = 1.35 V
First option
1.35
Programmable output common
Second option
1.50
mode voltage (applicable to Line
V
Third option
1.65
Outputs also)
Fourth option
1.8
Maximum programmable output
9
dB
level control gain
Programmable output level
1
dB
control gain step size
RL = 32
15
PO
Maximum output power
mW
RL = 16
30
Signal-to-noise ratio,
94
dB
A-weighted(4)
(3)
Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-
single-ended load.
(4)
Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.
6
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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