SLAS497C – AUGUST 2006 – REVISED DECEMBER 200" />
參數(shù)資料
型號: TLV320AIC31IRHBRG4
廠商: Texas Instruments
文件頁數(shù): 21/84頁
文件大?。?/td> 0K
描述: IC STEREO AUDIO CODEC LP 32-VQFN
標準包裝: 3,000
類型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 92 / 100
動態(tài)范圍,標準 ADC / DAC (db): 92 / 100
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
配用: 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
Decay Time
Input
Signal
Output
Signal
AGC
Gain
Attack
Time
STEREO AUDIO DAC
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
Figure 24. Typical Operation of the AGC Algorithm During Speech Recording
Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time
constants are achieved using the FSref value programmed in the control registers. However, if the FSref is set in
the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different
FSref in practice, then the time constants would not be correct.
The TLV320AIC31 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel
of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit digital
delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced
performance at low sampling rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the
audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × FSref and
changing the oversampling ratio as the input sample rate is changed. For an FSref of 48 kHz, the digital
delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated
within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly,
for an FSref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent FSref can be achieved by turning on PLL
Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled)
Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)
28
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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