SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ......................" />
參數(shù)資料
型號： TLV320AIC31IRHBRG4
廠商： Texas Instruments
文件頁數(shù)： 52/84頁
文件大?。?/td> 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
Output Stage Volume Controls
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output
stage network, connected to each of the analog signals that route to the output stage. In addition, to enable
completely independent mixing operations to be performed for each output driver, each analog signal coming into
the output stage may have up to seven separate volume controls. These volume controls all have approximately
0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations.
Table 5 lists the detailed gain versus programmed setting for this basic volume control.
Table 5. Output Stage Volume Control Settings and Gains
Gain Setting
Analog Gain
Gain Setting
Analog Gain
Gain Setting
Analog Gain
Gain Setting
Analog Gain
(dB)
0 0.0
30
-15.0
60
-30.1
90
-45.2
1
-0.5
31
-15.5
61
-30.6
91
-45.8
2
-1.0
32
-16.0
62
-31.1
92
-46.2
3
-1.5
33
-16.5
63
-31.6
93
-46.7
4
-2.0
34
-17.0
64
-32.1
94
-47.4
5
-2.5
35
-17.5
65
-32.6
95
-47.9
6
-3.0
36
-18.0
66
-33.1
96
-48.2
7
-3.5
37
-18.6
67
-33.6
97
-48.7
8
-4.0
38
-19.1
68
-34.1
98
-49.3
9
-4.5
39
-19.6
69
-34.6
99
-50.0
10
-5.0
40
-20.1
70
-35.1
100
-50.3
11
-5.5
41
-20.6
71
-35.7
101
-51.0
12
-6.0
42
-21.1
72
-36.1
102
-51.4
13
-6.5
43
-21.6
73
-36.7
103
-51.8
14
-7.0
44
-22.1
74
-37.1
104
-52.2
15
-7.5
45
-22.6
75
-37.7
105
-52.7
16
-8.0
46
-23.1
76
-38.2
106
-53.7
17
-8.5
47
-23.6
77
-38.7
107
-54.2
18
-9.0
48
-24.1
78
-39.2
108
-55.3
19
-9.5
49
-24.6
79
-39.7
109
-56.7
20
-10.0
50
-25.1
80
-40.2
110
-58.3
21
-10.5
51
-25.6
81
-40.7
111
-60.2
22
-11.0
52
-26.1
82
-41.2
112
-62.7
23
-11.5
53
-26.6
83
-41.7
113
-64.3
24
-12.0
54
-27.1
84
-42.2
114
-66.2
25
-12.5
55
-27.6
85
-42.7
115
-68.7
26
-13.0
56
-28.1
86
-43.2
116
-72.2
27
-13.5
57
-28.6
87
-43.8
117
-78.3
28
-14.0
58
-29.1
88
-44.3
118–127
Mute
29
-14.5
59
-29.6
89
-44.8
Page 0 / Register 45:
Reserved Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00000000
Reserved. Do not write to this register.
56
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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