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參數(shù)資料
型號： TLV320AIC31IRHBRG4
廠商： Texas Instruments
文件頁數(shù)： 55/84頁
文件大小： 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標準包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標準 ADC / DAC (db)： 92 / 100
動態(tài)范圍，標準 ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 56:
PGA_R to HPLCOM Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPLCOM
1: PGA_R is routed to HPLCOM
D6-D0
R/W
0000000
PGA_R to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5.
Page 0 / Register 57:
DAC_R1 to HPLCOM Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM
1: DAC_R1 is routed to HPLCOM
D6-D0
R/W
0000000
DAC_R1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5.
Page 0 / Register 58:
HPLCOM Output Level Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
HPLCOM Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
HPLCOM Mute
0: HPLCOM is muted
1: HPLCOM is not muted
D2
R/W
1
HPLCOM Power Down Drive Control
0: HPLCOM is weakly driven to a common-mode when powered down
1: HPLCOM is 3-stated when powered down
D1
R
1
HPLCOM Volume Control Status
0: Not all programmed gains to HPLCOM have been applied yet
1: All programmed gains to HPLCOM have been applied
D0
R/W
0
HPLCOM Power Control
0: HPLCOM is not fully powered up
1: HPLCOM is fully powered up
Page 0 / Register 59:
Reserved Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
0000000
Reserved. Write only '0000000' to this register.
Page 0 / Register 60:
PGA_L to HPROUT Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPROUT
1: PGA_L is routed to HPROUT
D6-D0
R/W
0000000
PGA_L to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5.
Copyright 2006–2008, Texas Instruments Incorporated
59
Product Folder Link(s): TLV320AIC31
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