參數(shù)資料
型號： TLV320AIC31IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 25/83頁
文件大?。?/td> 1197K
代理商： TLV320AIC31IRHBT
DIGITAL INTERPOLATION FILTER
DELTA-SIGMA AUDIO DAC
AUDIO DAC DIGITAL VOLUME CONTROL
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data are provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/FS. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (that is, 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and
still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The
interpolation filter is designed to maintain at least 65-dB rejection of images that land below 7.455 FS. In order to
utilize the programmable interpolation capability, the FSref should be programmed to a higher rate (restricted to be
in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual FS is set using the NDAC divider. For
example, if FS = 8 kHz is required, then FSref can be set to 48 kHz, and the DAC FS set to FSref/6. This ensures
that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
The stereo audio DAC incorporates a third order, multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a
continuous time RC filter. The analog FIR operates at a rate of 128 × FSref (6.144 MHz when FSref = 48 kHz,
5.6448 MHz when FSref = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.
The audio DAC includes a digital volume control block which implements a programmable digital gain. The
volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for
each channel. The volume level of both channels can also be changed simultaneously by the master volume
control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by
one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can
be slowed to one step per two input samples through a register bit.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the
desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is
enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this
flag is set, the internal soft-stepping process and power down sequence is complete, and the MCLK can then be
stopped if desired.
The TLV320AIC31 also includes functionality to detect when the user switches on or off the de-emphasis or
digital audio processing functions, to (1) soft-mute the DAC volume control, (2) change the operation of the digital
effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The
circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume
level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.
Copyright 2006–2008, Texas Instruments Incorporated
31
Product Folder Link(s): TLV320AIC31
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC31IRHBT 制造商:Texas Instruments 功能描述:IC CODEC STEREO AUDIO 32-VQFN
TLV320AIC31IRHBTG4 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC32 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
TLV320AIC32_07 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
TLV320AIC3204 制造商:TI 制造商全稱:Texas Instruments 功能描述:Ultra Low Power Stereo Audio Codec
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