參數(shù)資料
型號: TLV320AIC32IRHB
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, PLASTIC, QFN-32
文件頁數(shù): 40/76頁
文件大?。?/td> 1124K
代理商: TLV320AIC32IRHB
www.ti.com
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
Page 0 / Register 23:
LINE2R to Right ADC Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
0:
Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1:
Right ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1–D0
R
00
Reserved. Write only zeros to these register bits
Page 0 / Register 24:
LINE1L to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Reserved. Write Only zero to this bit.
D6–D3
R/W
1111
LINE1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the right ADC PGA
D2–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
D5–D3
R
000
Reserved. Write only zeros to these register bits.
D2–D0
R
XXX
Reserved. Write only zeros to these register bits.
Page 0 / Register 26:
Left AGC Control Register A
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Left AGC Enable
0: Left AGC is disabled
1: Left AGC is enabled
D6–D4
R/W
000
Left AGC Target Gain
000: Left AGC target gain = –5.5-dB
001: Left AGC target gain = –8-dB
010: Left AGC target gain = –10-dB
011: Left AGC target gain = –12-dB
100: Left AGC target gain = –14-dB
101: Left AGC target gain = –17-dB
110: Left AGC target gain = –20-dB
111: Left AGC target gain = –24-dB
D3–D2
R/W
00
Left AGC Attack Time
These time constants(1) will not be accurate when double rate audio mode is enabled.
00: Left AGC attack time = 8-msec
01: Left AGC attack time = 11-msec
10: Left AGC attack time = 16-msec
11: Left AGC attack time = 20-msec
(1)
Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
45
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