參數(shù)資料
型號： TLV320AIC32IRHB
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, PLASTIC, QFN-32
文件頁數(shù)： 44/76頁
文件大?。?/td> 1124K
代理商： TLV320AIC32IRHB
www.ti.com
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
Page 0 / Register 35:
Right AGC Noise Gate Debounce Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D3
R/W
00000
Right AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
Page 0 / Register 36:
ADC Flag Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R
0
Left ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D6
R
0
Left ADC Power Status
0: Left ADC is in a power down state
1: Left ADC is in a power up state
D5
R
0
Left AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D4
R
0
Left AGC Saturation Flag
0: Left AGC is not saturated
1: Left AGC gain applied = maximum allowed gain for left AGC
D3
R
0
Right ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D2
R
0
Right ADC Power Status
0: Right ADC is in a power down state
1: Right ADC is in a power up state
D1
R
0
Right AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D0
R
0
Right AGC Saturation Flag
0: Right AGC is not saturated
1: Right AGC gain applied = maximum allowed gain for right AGC
Page 0 / Register 37:
DAC Power and Output Driver Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Left DAC Power Control
0: Left DAC not powered up
1: Left DAC is powered up
D6
R/W
0
Right DAC Power Control
0: Right DAC not powered up
1: Right DAC is powered up
D5–D4
R/W
00
HPLCOM Output Driver Configuration Control
00: HPLCOM configured as differential of HPLOUT
01: HPLCOM configured as constant VCM output
10: HPLCOM configured as independent single-ended output
11: Reserved. Do not write this sequence to these register bits.
D3–D0
R
000
Reserved. Write only zeros to these register bits.
49
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