參數(shù)資料
型號: TLV320AIC32IRHB
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, PLASTIC, QFN-32
文件頁數(shù): 47/76頁
文件大?。?/td> 1124K
代理商: TLV320AIC32IRHB
www.ti.com
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
Page 0 / Register 41:
DAC Output Switching Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high power output drivers (1)
11: Reserved. Do not write this sequence to these register bits.
D3–D2
R/W
00
Reserved. Write only zeros to these bits.
D1–D0
R/W
00
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D4
R/W
0000
Output Driver Power-On Delay Control
0000: Driver power-on time = 0-
sec
0001: Driver power-on time = 10-
sec
0010: Driver power-on time = 100-
sec
0011: Driver power-on time = 1-msec
0100: Driver power-on time = 10-msec
0101: Driver power-on time = 50-msec
0110: Driver power-on time = 100-msec
0111: Driver power-on time = 200-msec
1000: Driver power-on time = 400-msec
1001: Driver power-on time = 800-msec
1010: Driver power-on time = 2-sec
1011: Driver power-on time = 4-sec
1100–1111: Reserved. Do not write these sequences to these register bits.
D3-D2
R/W
00
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0-msec
01: Driver ramp-up step time = 1-msec
10: Driver ramp-up step time = 2-msec
11: Driver ramp-up step time = 4-msec
D1
R/W
0
Weak Output Common-mode Voltage Control
0:
Weakly driven output common-mode voltage is generated from bandgap reference
1:
Weakly driven output common-mode voltage is generated from resistor divider off the AVDD
supply
D0
R/W
0
Reserved. Write only zero to this register bit.
Page 0 / Register 43:
Left DAC Digital Volume Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
1
Left DAC Digital Mute
0: The left DAC channel is not muted
1: The left DAC channel is muted
D6–D0
R/W
0000000
Left DAC Digital Volume Control Setting
0000000: Gain = 0.0-dB
0000001: Gain = –0.5-dB
0000010: Gain = –1.0-dB
1111101: Gain = –62.5-dB
1111110: Gain = –63.0-dB
1111111: Gain = –63.5-dB
51
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