參數(shù)資料
型號(hào)： TMP320F2810PGFS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 56/103頁
文件大小： 1341K
代理商： TMP320F2810PGFS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
56
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PERIPHERALS
The integrated peripherals of the TMS320F2810 and TMS320F2812 are described in the following subsections:
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Controller area network (CAN) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
PLL-based clock module
Digital I/O and shared pin functions
External memory interfaces (TMS320F2812 only)
Watchdog (WD) timer module
32-bit CPU-Timers 0/1/2
This section describes the three 32-bit CPU-timers on the F2810 and F2812 devices (TIMER0/1/2).
CPU-Timers 1 and 2 are reserved for the Real-Time OS (such as DSP-BIOS).
CPU-Timer 0 can be used in
user applications.
Borrow
Reset
Timer Reload
SYSCLKOUT
TCR.4
(Timer Start Status)
TINT
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
16-Bit Prescale Counter
PSCH:PSC
Borrow
NOTE A: The CPU-Timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB).
Figure 12. CPU-Timers
P
If the application is not using BIOS, then CPU-Timers 1 and 2 can be used in the application.
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