參數(shù)資料
型號(hào)： TMP320F2810PGFS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 8/103頁
文件大小： 1341K
代理商： TMP320F2810PGFS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions
Table 2 specifies the signals on the F2810 and F2812 devices. All digital inputs are TTL-compatible. All outputs
are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 20-
μ
A resistor is used for pullup/down.
Table 2. Signal Descriptions
NAME
PIN NO.
I/O/Z
DRIVE
PU/PD
DESCRIPTION
XINTF SIGNALS (2812 ONLY)
XA[18:0]
O/Z
19-bit Address Bus
XD[15:0]
I/O/Z
16-bit Data Bus
XMP/MC
I
PU
Microprocessor/Microcomputer Mode Select
XHOLD
I
PU
External DMA Hold Request
XHOLDA
O/Z
External DMA Hold Acknowledge
XZCS0
O/Z
Zone 0 Chip Select Strobe
XZCS1
O/Z
Zone 1 Chip Select Strobe
XZCS2
O/Z
Zone 2 Chip Select Strobe
XZCS6AND7
O/Z
Zone 6 and 7 Chip Select Strobe
XWE
O/Z
Write Enable
XRD
O/Z
Read Enable
XRNW
O/Z
Read Not Write Select
XREADY
I
PU
Input Ready Signal
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
I
–
Oscillator Input Or Clock Generator Input
X2
I
–
Oscillator Output
XPPLDIS
I
PU
Disable PLL When High
TESTSEL
I
PU
Test Mode Select Signal
XRS
I/O
PU
Device Reset (in) and Watchdog Reset (out)
TEST1
I/O
–
Flash Test Signal 1
TEST2
I/O
–
Flash Test Signal 2
JTAG
TRST
I
PD
JTAG Test-Logic Reset
TCK
I
JTAG Test clock
TMS
I
JTAG Test Mode Select
TDI
I
JTAG Test Data Input
TDO
O/Z
JTAG Test Data Output
EMU0
I/O/Z
PU
Emulation/Test trigger channel 0
EMU1
I/O/Z
PU
Emulation/Test trigger channel 1
PU = pin has internal pullup; PD = pin has internal pulldown
P
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