Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
9
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* I
u
indicates an internal pull-up; I
d
indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will
tolerate 5 V at their inputs.
Pin
185
Symbol
TDI
Type*
I
u
Name/Description
Boundary-Scan Input Data.
This pin has an internal 20 k
pull-up
resistor.
Boundary-Scan Mode Select.
This pin has an internal 20 k
pull-up
resistor.
Boundary-Scan Reset (Active-Low).
This pin has an internal 20 k
pull-down resistor.
Boundary-Scan Output Data.
Transmit STS-1 Clock.
The STS-1 clock can be 51.84 MHz for serial
input data, or 19.44 MHz or 6.48 MHz for byte-wide data.
Transmit STS-1 Sync.
The STS-1 sync pulse can be either J0 for
8 kHz only or a composite of J0J1V1 for 2 kHz.
Transmit STS-1 Data.
In the byte-wide output mode, this is bit 6—bit 0
of the data bus. TSTS1DATA7 is the most significant bit of the output
byte.
Transmit STS-1 Parity.
The parity output is only defined for byte-wide
data. The device can be provisioned to source either an odd or even
parity.
Transmit STS-1 Serial Data/Transmit STS-1 Data Bit 7 (MSB).
In
serial mode, this pin provides 51.84 Mbits/s serial data. In parallel
mode, this pin provides TSTS1DATA7.
Transmit STS-1 Output Clock.
Receive STS-1 Clock.
The STS-1 clock can be 51.84 MHz for serial
input data, or 19.44 MHz or 6.48 MHz for byte-wide data.
Receive STS-1 Data.
In the byte-wide input mode, this is the data bus
with RSTS1DATA7 as the most significant bit of the input byte. This pin
has an internal 100 k
pull-up resistor.
Receive STS-1 Parity.
The parity input is only defined for byte-wide
data. The device can be provisioned to accept either an odd or even
parity. This pin has an internal 100 k
pull-up resistor.
Receive STS-1 Serial Data.
If the device is operating in the serial
mode, then RSTS1SERIAL is used as the input data pin. In the bus
mode, this pin is used to synchronize byte 1 of 3 (see Figure 15,
page 71).
In-Circuit Test Control (Active-Low).
If ICT is forced low, all output
pins are placed in the high-impedance state. This pin has an internal
20 k
pull-up resistor.
Ground Reference for Digital Circuitry.
186
TMS
I
u
188
TRST
I
d
189
89
TDO
O
I
TSTS1CLKIN
90
TSTS1SYNC
I
92,
94—99
TSTS1DATA[6:0]
O
100
TSTS1PAR
O
91
TSTS1SERIAL/
TSTS1DATA7
O
88
82
TSTS1CLKOUT
RSTS1CLK
O
I
80, 78—75,
73—71
RSTS1DATA[7:0]
I
u
70
RSTS1PAR
I
u
85
RSTS1SERIAL
I
156
ICT
I
u
1, 2, 21, 31,
51, 53, 54, 74,
79, 81, 84,
103, 105, 125,
135, 155, 157,
158, 177, 182,
187, 207
12, 26, 40, 52,
65, 69, 83, 93,
104, 111, 116,
121, 130, 144,
150, 168, 196
V
SS
I
V
DD
I
Power Supply for Digital Circuitry.