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| 型號(hào)： | TMPR28051-3-SL5 |
| 英文描述： | Paired Cable; Number of Conductors:12; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyolefin; Number of Pairs:6; Impedance:100ohm; Voltage Nom.:300V RoHS Compliant: Yes |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 25/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051-3-SL5 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
11
Lucent Technologies Inc.
DS1/E1 to STS-1 Block Descriptions
(continued)
Input Select Logic
(continued)
The value of 11111 will cause the internally generated
test pattern to be inserted for that VT slot.
There are no restrictions on the number of VT slots that
any given DS1/E1 input can supply (e.g., up to 28
VT1.5 slots can select the same DS1 input).
This block can also be used to insert the test pattern
(see Test Pattern Insert section on page 19).
Elastic Store
The selected DS1/E1 clock and data signals are fed to
an elastic store that is used to synchronize the incom-
ing DS1/E1 to the local STS-1 clock. This block deter-
mines the need for positive/zero/negative (P/Z/N)
stuffing for each input. Data that is transmitted from this
block is synchronized to the local transmit STS-1 clock
(TSTS1CLK). This block allows the device to accept
DS1 signals at 1.544 Mbits/s ± 130 ppm with up to ±5
unit intervals peak jitter, or E1 signals at 2.048 Mbits/s
± 130 ppm with up to ±5 unit intervals peak jitter.
VT Generate
This block generates the VT superframe. Unless AIS-V
is being forced, the superframe is built with a fixed out-
put pointer value of decimal 78 in all the VT1.5 slots.
The VT size field is set to 11 binary, and the new data
flag is set to 0110 binary. This corresponds to 0x6C4E
for the V1 and V2 bytes within the VT1.5 superframe.
Also, unless AIS-V is being forced, the superframe is
built with a fixed output pointer value of decimal 105 in
all the VT2 slots. The VT size field is set to 10 binary,
and the new data flag is set to 0110 binary. This corre-
sponds to 0x6869 for the V1 and V2 bytes within the
VT2 superframe.
In this block, the DS1/E1 data is placed into the VT,
and the VT overhead is generated. The format of the
VT overhead byte, V5, is shown in Table 2.
Table 2. VT1.5 Overhead Byte Format (V5)
Each VT can be provisioned to insert AIS-V by assign-
ing VTAISINS[1:28] = 1 in registers 0x4F—0x6A (bit 3).
AIS-V consists of overwriting the entire VT payload and
overhead with ones.
RDI-V can be automatically inserted by the device
(VTRFIRDIEN[1:28] = 1 in registers 0x4F—0x6A, bit 6)
or written into the V5 byte under control of the micro-
processor (VTRFIRDIEN[1:28] = 0 in registers
0x4F—0x6A, bit 6). In the automatic mode, the values
for bit 4 (RFI-V) and bit 8 (RDI-V) are defined in
Table 3. The automatic insertion mode may not meet
the different standards body requirements unless the
VT PTE at both ends of the path (and any intermediate
NEs provisioned to perform intermediate-path PM on
that path) support the protocol defined in Table 3. To
meet the different standards requirements, the micro-
processor mode allows programming the RDI-V and
RFI-V bits in registers 0x4F—0x6A by programming
VTRFIINS[1:28] (bit 5) and VTRDIINS[1:28] (bit 4),
respectively.
Table 3. RFI-V, RDI-V Description
The VT label for each VT is also provisionable through
the microprocessor by programming the
VTLABINS[2:0]_[1:28] in registers 0x4F—0x6A, bit 2
through bit 0.
Bit #
1
BIP-2
2
3
4
5
6
7
8
REI-V
RFI-V
Signal
Label
RDI-V
Bit 4
0
0
1
1
Bit 8
0
1
0
1
Description
No alarm
AIS-V or LOP-V
VT payload mismatch
VT unequipped
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