參數(shù)資料
型號: TMPR28051-3-SL5
英文描述: Paired Cable; Number of Conductors:12; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyolefin; Number of Pairs:6; Impedance:100ohm; Voltage Nom.:300V RoHS Compliant: Yes
中文描述: TMPR28051 STS-1/AU-3(的STM - 0)映射為版本的設(shè)備5設(shè)備咨詢
文件頁數(shù): 69/90頁
文件大?。?/td> 1090K
代理商: TMPR28051-3-SL5
Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
55
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Register Architecture Description
(continued)
Table 25. Register 0x91: STS-1 LOS Detect/Test Pattern Edge Control
Address
(Hex)
Bit #
Name
Function
Reset
Default
(Hex)
0x00
0x91
The bits in register 0x91 are used to set the number of
6.48 MHz clock periods required to declare received STS-1
loss of signal. The two least significant bits have a dual pur-
pose and can also be used to program the edge on which
the QRSS pattern generator and detector data is clocked.
If this value is 0x00, then LOS is not declared; otherwise,
the device looks for an all-zeros or all-ones input signal for
the binary equivalent of this value in clock periods to
declare LOS.
These bits are used to set the number of 6.48 MHz clock
periods required to declare received STS-1 loss of signal.
7
6
5
4
3
2
1
LOSDET-7
LOSDET-6
LOSDET-5
LOSDET-4
LOSDET-3
LOSDET-2
LOSDET-1/
TP_EDGE-1
This bit has a dual purpose. It can either contribute to the
above count or can be programmed to set the edge on
which the test pattern detector data is clocked in. When set
to 0, the detector uses the rising edge of the selected input
clock to retime the data, or uses the falling edge otherwise.
This bit has a dual purpose. It can either contribute to the
above count or can be programmed to set the edge on
which the test pattern generator data is clocked out. When
set to 0, the generator uses the rising edge of the blue sig-
nal clock to retime the data, or uses the falling edge other-
wise.
Reserved.
0
LOSDET-0/
TP_EDGE-0
0x92—0xBE
7—0
Value is
0.
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