參數(shù)資料
型號： TMS279XN
廠商： Texas Instruments, Inc.
英文描述： FLOPPY DISK FORMATTERICONTROLLER FAMILY
中文描述： 軟盤驅(qū)動FORMATTERICONTROLLER家庭
文件頁數(shù)： 2/40頁
文件大?。?/td> 334K
代理商： TMS279XN
TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY
2
pin descriptions
PIN
NUMBER
1
PIN NAME
SYMBOL
FUNCTION
ENABLE PRECOMP
ENP
A Logic high on this input enables write precompensation to
be performed on double density Write Data output only.
19
MASTER RESET#
MR#
A logic low (50 microseconds min.) on this input resets the
device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When MR#
is brought to a logic high a RESTORE Command is executed,
regardless of the state of the Ready signal from the drive.
Also, HEX 01 is loaded into sector register.
20
POWER SUPPLIES
VSS
Ground
21
VCC
+5V ±5%
COMPUTER INERFACE
A logic low on this input gates data on the DAL into the
selected register when CS# is low.
2
WRITE ENABLE#
WE#
3
CHIP SELECT#
CS#
A logic low on this input selects the chip and enables
computer communication with the device.
4
READ ENABLE#
RE#
A logic low on this input controls the placement of data from a
selected register on the DAL when CS# is low.
5,6
REGISTER SELECT
LINE
A0, A1
These inputs select the register to receive / transfer data on
the DAL lines under RE# and WE# control:
CS#
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
RE#
Status Reg
Track Reg
Sector Reg
Data Reg
WE#
Command Reg
Track Reg
Sector Reg
Data Reg
7-14
DATA ACCESS LINES
DALO-
DAL7
Eight bit bi-directional bus used for transfer of commands,
status, and data. These lines are inverted (active low) on
TMS2791 and TMS2795.
24
CLOCK
CLK
This input requires a free-running 50% duty cycle square wave
clock for internal timing reference, 2 MHz ± 1 % for 8" drives, 1
MHz ± 1 % for mini-floppies.
38
DATA REQUEST
DRQ
This output indicates that the Data Register contains
assembled data in Read operations, or the DR is empty in
Write operations. This signal is reset when serviced by the
computer through reading or loading the DR.
39
INTERRUPT
REQUEST
INTRQ
This output is set at the completion of any command and is
reset when the Status register is read or the Command
register is written to.
FLOPPY DISK INTERFACE
STEP
The step output contains a pulse for each step.
15
STEP
16
DIRECTION
DIRC
Direction Output is active high when stepping in, active low
when stepping out.
17
5 1/4”, 8" SELECT
5#/8
This input selects the internal VCO frequency for use with
51/4" drives or 8" drives.
相關(guān)PDF資料
PDF描述
TMS27C040-15 Programmable Read-Only Memory(512K×8結(jié)構(gòu),可擦可編程只讀存儲器)
TMS27C256-150 Programmable Read-Only Memory(32K×8結(jié)構(gòu),可擦可編程只讀存儲器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS27C/PC256-10 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-12 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-15 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-17 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C/PC256-20 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
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