參數(shù)資料
型號: TMS279XN
廠商: Texas Instruments, Inc.
英文描述: FLOPPY DISK FORMATTERICONTROLLER FAMILY
中文描述: 軟盤驅(qū)動FORMATTERICONTROLLER家庭
文件頁數(shù): 40/40頁
文件大?。?/td> 334K
代理商: TMS279XN
TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY
40
status for type II and III commands
BIT NAME
MEANING
S 7 NOT READY
This bit when set indicates the drive is not ready. When reset, it indicates that the
drive is ready. This bit is an inverted copy of the ready input and 'ORed' with MR.
The Type II and III commands will not execute unless the drive is ready.
S6 WRITE PROTECT
On read record: not used. On read track: not used. On any write: it indicates a
write protect. This bit is reset when updated.
S5 RECORD TYPE
On read record: it indicates the record-type code from data field address mark.
1 = deleted data mark. 0 = data mark. On any write: forced to a zero.
S4 RECORD NOT FOUND
(RNF)
When set, it indicates that the desired track, sector, or side were not found. This
bit is reset when updated.
S3 CRC ERROR
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error
in data field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates the computer did not respond to DRQ in one byte time. This
bit is reset to zero when updated.
S1 DATA REQUEST
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a read
operation or the DR is empty on a write operation. This bit is reset to zero when
updated.
S0 BUSY
When set, command is under execution. When reset, no command is under
execution.
summary of adjustment procedure
NOTE: To maintain internal VCO operation, ensure that TEST# = 1 whenever a master reset pulse is applied.
WRITE PRECOMPENSATION
1) Set TEST# (pin 22) to a logic high.
2) Strobe MR# (pin 19).
3) Set TEST# (pin 22) to a logic low.
4) Observe pulse duration on WD (pin 31).
5) Adjust WPW (pin 33) for desired pulse duration (precompensation value).
6) Set TEST# (pin 22) to a logic high.
DATA SEPARATOR
1) Set TEST# (pin 22) to a logic high.
2) Strobe MR# (pin 19). Ensure that 5#/8, and DDEN# are set properly.
3) Set TEST# (pin 22) to a logic low.
4) Observe pulse duration on TG43 (pin 29).
5) Adjust RPW (pin 18) for 1/8 of the read clock (250 ns for 8 " DD, 500 ns for 5'1/4" DD, etc.).
6) Observe frequency on DIRC (pin 161.
7) Adjust variable capacitor on VCO pin for data rate (500 kHz for 8" DD, 250 kHz for 5 1/4" DD, etc.).
8) Set TEST# (pin 22) to a logic high.
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