參數(shù)資料
型號(hào)： TMS279XN
廠(chǎng)商： Texas Instruments, Inc.
英文描述： FLOPPY DISK FORMATTERICONTROLLER FAMILY
中文描述： 軟盤(pán)驅(qū)動(dòng)FORMATTERICONTROLLER家庭
文件頁(yè)數(shù)： 20/40頁(yè)
文件大小： 334K
代理商： TMS279XN
TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY
20
The Type II and Ill commands for the 2795-97 contain a side select flag (bit 1). When U = 0, SSO is updated
to 0. Similarly, U = 1 updates SSO to 1. The chip compares the SSO to the ID field. If they do not compare
within 5 revolutions, the interrupt line is made active and the RNF status bit is set.
The 2795/7 Read Sector and Write Sector commands include a 'L' flag. The 'L' flag, in conjunction with the
sector length byte of the ID field, allows different byte lengths to be implemented in each sector. For IBM
compatibility, the 'L' flag should be set to a one.
read sector
Upon receipt of the Read Sector command, the head is loaded, the busy status bit set, and when an ID field
is encountered that has the correct track number, correct sector number, correct side number, and correct
CRC, the data field is presented to the computer The data address mark of the data field must be found
within 30 bytes in single density and 43 bytes in double density of the last ID field CRC byte; if not, the ID
field search is repeated.
When the first character or byte of the data field has been shifted through the DSR, it is transferred to the
DR, and DRO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and
another DRQ is generated. if the computer has not read the previous contents of the DR before a new
character is transferred that character is lost and the lost data status bit is set. This sequence continues until
the complete data field has been inputted to the computer. If there is a CRC error at the end of the data field,
the CRC error status bit is set, and the command is terminated (even if it is a multiple sector command).
At the end of the read operation, the type of data address mark encountered in the data field is recorded in
the status register (bit 5) as shown:
STATUS
BIT 5
1
0
Deleted Data Mark
Data Mark
write sector
Upon receipt of the Write Sector command, the head is loaded (HLD active) and the busy status bit is set.
When an ID field is encountered that has the correct track number, correct sector number, correct side
number, and correct CRC, a DRQ is generated. The 279X counts off 11 bytes in single density and 22 bytes
in double density from the CRC field and the write gate (WG) output is made active if the DRO is serviced
(i.e., the DR has been loaded by the computer). If DRQ has not been serviced, the command is terminated
and the lost data status bit is set. If the DRQ has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are then written on the disk. At this time the data
address mark is then written on the disk as determined by the a0 field of the command as shown below:
a0
1
0
Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark
The 279X then writes the data field and generates DRQ's to the computer. If the DRQ is not serviced in time
for continuous writing, the lost data status bit is set and a byte of zeroes is written on the disk. The command
is not terminated. After the last data byte has been written on the disk, the two-byte CRC is computed
internally and written on the disk followed by one byte of FE in FM or in MFM. The WG output is then
deactivated. For a 2 MHz clock, the INTRO will set 8 to 12 its after the last CRC byte is written. For partial
sector writing, the proper method is to write the data and fill the balance with zeroes. By letting the chip fill
the zeroes, errors may be masked by the lost data status and improper CRC bytes.
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