參數(shù)資料
型號： TMS320C10-14
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 38/139頁
文件大小： 1478K
代理商： TMS320C10-14
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
38
MEMORY READ AND INSTRUCTION TIMING
switching characteristics over recommended operating conditions
PARAMETER
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
tsu(A)R
tsu(A)W
th(A)
ten(D)W
tsu(D)W
th(D)W
tdis(D)W
tw(WEL)
tw(RENL)
trec(WE)
trec(REN)
td(WE-CLK)
Values were derived from characterization data and not tested.
Address bus valid before REN
↓
Address bus valid before WE
↓
0.25 tc(C)–39
0.50 tc(C)–45
5
ns
ns
Address bus valid after REN
↑
or WE
↑
ns
Data starts being driven before WE
↓
0.25 tc(C)
ns
Data valid prior to WE
↓
0.25 tc(C)–45
0.25 tc(C)–10
ns
Data valid after WE
↑
ns
Data in high impedance after WE
↑
0.25 tc(C) + 25
ns
WE-low duration
0.50 tc(C)–15
0.75 tc(C)–15
0.25 tc(C)–5
0.50 tc(C)–10
0.50 tc(C)–15
ns
REN-low duration
ns
Write recovery time, time between WE
↑
and REN
↓
ns
Read recovery time, time between REN
↑
and WE
↓
ns
Time from WE
↑
to CLKOUT
↑
ns
timing requirements over recommended operating conditions
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tsu(D)R
th(D)R
Data set-up prior to REN
↑
Data hold after REN
↑
52
ns
0
ns
ta(A)
Access time for read cycle data
valid after valid address
tc(C)–90
ns
toe(REN)
tdis(D)R
Access time for read cycle from REN
↓
0.75 tc(C)–60
0.25 tc(C)
ns
Data in high impedance after REN
↑
ns
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER
Delay from RS
↓
to REN
↑
and WE
↑
Delay from RS
↓
to REN and
WE into high impedance
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ns
td(RS-RW)
0.75 tc(C) + 20
tdis(RS-RW)
1.25 tc(C)
ns
tdis(RS-DB)
tdis(RS-AB)
ten(RS-AB)
Data bus disable after RS
↓
1.25 tc(C)
tc(C)
tc(C)
ns
Address bus disable after RS
↓
ns
Address bus enable after RS
↑
ns
timing requirements over recommended operating conditions
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tsu(RS)
tw(RS)
RS setup prior to CLKOUT
↓
(see Note 10)
60
ns
RS pulse duration
5tc(C)
ns
NOTE 10: RS can occur anytime during the clock cycle. Time given is minimum to ensure synchronous operation.
相關(guān)PDF資料
PDF描述
TMS320C10-25 Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
TMS320C15-25 Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
TMS320LC17 Digital Signal Processors(278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
TMS320C203(中文) Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進的外圍，多種PLL可選)
TMS320VC203(中文) Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進的外圍，多種PLL可選)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C10-14FNL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
TMS320C10-25 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS
TMS320C10-25FNL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
TMS320C10FNA 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS
TMS320C10FNL 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*