參數(shù)資料
型號: TMS320C10-25
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的DSP)
中文描述: 數(shù)字信號處理器(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的數(shù)字信號處理器)
文件頁數(shù): 31/139頁
文件大?。?/td> 1478K
代理商: TMS320C10-25
I/O/Z
TMS320C10-14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
31
TERMINAL FUNCTIONS (concluded)
PIN
DESCRIPTION
NAME
NO.
SUPPLY/OSCILLATOR SIGNALS
CLKOUT
19
O
System clock output (one fourth CLKIN frequency).
VCC
VSS
CLKIN
4,33
I
5-V supply pins.
3,34
I
Ground pins.
24
I
Master clock input from external clock source.
SERIAL PORT AND TIMER SIGNALS
RXD
48
I
Asynchronous mode receive input.
TXD
47
O/Z
Asynchronous mode transmit output.
TCLK1
10
I
Timer 1 clock. If external clock is selected, it serves as clock input to Timer 1.
TCLK2
11
I
Timer 2 clock. If external clock is selected, it serves as clock input to Timer 2.
WDT
23
O
Watchdog timer output. An active low is generated on this pin when the watchdog timer times out.
BIT I/O PINS
IOP15
IOP14
IOP13
IOP12
IOP11
IOP10
IOP9
IOP8
IOP7
IOP6
IOP5
IOP4
IOP3
IOP2
IOP1
IOP0
MSB
LSB
29
30
31
32
37
38
41
42
44
45
51
52
53
54
55
56
I/O
16 bit I/O lines that can be individually configured as inputs or outputs and also individually set or
reset
when configured as outputs.
COMPARE AND CAPTURE SIGNALS
CMP0
CMP1
CMP2
CMP3
8
7
2
1
O
Compare outputs. The states of these pins are determined by the combination of compare and action
registers.
CAP0
CAP1
68
67
I
Capture inputs. A transition on these pins causes the timer register to be captured in FIFO stack.
CMP4/CAP2
66
I/O
This pin can be configured as compare output or capture input.
CMP5/CAP3
65
I/O
This pin can be configured as compare output or capture input.
Input/Output/High-impedance state.
相關PDF資料
PDF描述
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