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| 型號： | TMS320C240PQL |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 36/105頁 |
| 文件大?。?/td> | 1481K |
| 代理商： | TMS320C240PQL |
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TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
central arithmetic logic unit
The TMS320x240 central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate
it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).
Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or
derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform
Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the
CALU is always provided from the accumulator, and the other input can be provided from the product register
(PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the
ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320x240 devices support floating-point operations for applications requiring a large dynamic range.
The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator
by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Logical operations cannot result in
overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch
on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides
the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It also is useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
相關PDF資料 |
PDF描述 |
|---|---|
| TMS320C240PQQ | 16-Bit Microcontroller |
| TMS320F240PQL | 16-Bit Microcontroller |
| TMS320F240PQQ | 16-Bit Microcontroller |
| TMS320F240PQS | 16-Bit Microcontroller |
| TMS320LC31-40 | Digital Signal Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320C240PQQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMS320C241 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C241FNS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C241PGS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLER |
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