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SPI MASTER MODE TIMING PARAMETERS
SPI master mode timing information is listed in the following tables.
SPI master mode external timing parameters (clock phase = 0)
(see Figure 43)
WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
UNIT
MIN
4tc
MAX
128tc
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
MIN
5tc
MAX
127tc
tc(SPC)M
tw(SPCH)M§
tw(SPCL)M§
tw(SPCL)M§
tw(SPCH)M§
Cycle time, SPICLK
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M–70
0.5tc(SPC)M–70
0.5tc(SPC)M–70
0.5tc(SPC)M–70
0.5tc(SPC)M–0.5tc–70
0.5tc(SPC)M–0.5tc–70
0.5tc(SPC)M+0.5tc–70
0.5tc(SPC)M+0.5tc–70
0.5tc(SPC)M –0.5tc
0.5tc(SPC)M –0.5tc
0.5tc(SPC)M + 0.5tc
0.5tc(SPC)M + 0.5tc
ns
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SIMO)M§
Delay time, SPICLK high (clock polarity = 0) to
SPISIMO valid
– 10
10
– 10
10
ns
td(SPCL-SIMO)M§
Delay time, SPICLK low (clock polarity = 1) to
SPISIMO valid
– 10
10
– 10
10
tv(SPCL-SIMO)M§
Valid time, SPISIMO data valid after SPICLK low
(clock polarity =0)
0.5tc(SPC)M–70
0.5tc(SPC)M+0.5tc–70
ns
tv(SPCH-SIMO)M§
Valid time, SPISIMO data valid after SPICLK high
(clock polarity =1)
0.5tc(SPC)M–70
0.5tc(SPC)M+0.5tc–70
tsu(SOMI-SPCL)M§
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
0
0
ns
tsu(SOMI-SPCH)M§
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
0
0
tv(SPCL-SOMI)M§
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0.25tc(SPC)M–70
0.5tc(SPC)M–0.5tc–70
ns
tv(SPCH-SOMI)M§
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.25tc(SPC)M–70
0.5tc(SPC)M–0.5tc–70
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).