參數(shù)資料
型號(hào)： TMS320C242FNS
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 24/66頁
文件大小： 803K
代理商： TMS320C242FNS
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock domains (continued)
Two control bits, LPM(1) and LPM(0), specify which of the three possible low-power modes is entered when
the IDLE instruction is executed (see Table 7). These bits are located in the System Control and Status Register
(SCSR) described in the TMS320F243,F241,C242 DSP Controllers System and Peripherals User’s Guide
Volume 2 (literature number SPRU276).
Table 7. Low-Power Modes Summary
LOW-POWER MODE
LPMx BITS
SCSR[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
EXIT
CONDITION
CPU running normally
XX
On
On
On
On
On
—
IDLE1 – (LPM0)
00
Off
On
On
On
On
Peripheral Interrupt,
External Interrupt,
Reset
IDLE2 – (LPM1)
01
Off
Off
On
On
On
Wakeup Interrupts,
External Interrupt,
Reset
HALT – (LPM2)
{PLL/OSC power down}
1X
Off
Off
Off
Off
Off
Reset Only
wakeup from low-power modes
reset
A reset (from any source) causes the device to exit any of the IDLE modes. If the device is halted, the reset will
first start the oscillator, and there can be a delay while the oscillator powers up before clocks are generated to
initiate the CPU reset sequence.
external interrupts
The external interrupts, XINTx, can cause the device to exit any of the low-power modes, except HALT. If the
device is in IDLE2 mode, the synchronous logic connected to the external interrupt pins is bypassed with
combinatorial logic which recognizes the interrupt on the pin, starts the clocks, and then allows the clocked logic
to generate an interrupt request to the PIE controller. Note that in Table 7, external interrupts include PDPINT.
A
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