參數(shù)資料
型號(hào)： TMS320C242FNS
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 33/66頁(yè)
文件大小： 803K
代理商： TMS320C242FNS
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PWM characteristics
Characteristics of the PWMs are as follows:
16-bit registers
Programmable deadband for the PWM output pairs, from 0 to 24 s
Minimum deadband width of 50 ns
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
Minimized CPU overhead using auto-reload of the compare and period registers
capture unit
The capture unit provides a logging function for different events or transitions. The values of the GP timer 2
counter are captured and stored in the two-level FIFO stacks when selected transitions are detected on capture
input pins, CAPx for x = 1, 2, or 3. The capture unit of the TMS320x24x consists of three capture circuits.
Capture units include the following features:
–
One 16-bit capture control register, CAPCON (R/W)
–
One 16-bit capture FIFO status register, CAPFIFO
–
Selection of GP Timer 2 as the time base
–
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
–
Three Schmitt-triggered capture input pins CAP1, CAP2, and CAP3, one input pin per each capture
unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the
input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1 and
CAP2 can also be used as QEP inputs to the QEP circuit.]
–
User-specified transition (rising edge, falling edge, or both edges) detection
–
Three maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2) can be used to interface the on-chip QEP circuit with a quadrature
encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse
sequence is detected, and GP timer 2 is incremented or decremented by the rising and falling edges of the two
input signals (four times the frequency of either input pulse).
A
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