參數(shù)資料
型號(hào): TMS320C242PGA
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 57/66頁(yè)
文件大小: 803K
代理商: TMS320C242PGA
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
MAX
10
UNIT
VCCA = 5.5 V
5 5 V
Converting
mA
ICCA
Analogsupplycurrent
Analog supply current
Non-converting
2
VCCA = VREFHI = 5.5 V
PLL or OSC power
down
1
A
Cai
Analoginp tcapacitance
Analog input capacitance
Typical capacitive load on
Ty ical ca acitive load on
analog input pin
Non-sampling
10
pF
Sampling
30
EDNL
Differential nonlinearity error
Difference between the actual step width and the ideal
value
2
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight line through
the ADC transfer characteristics, excluding the
quantization error
2
LSB
td(PU)
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
s
ZAI
Analog input source impedance
Analog input source impedance for conversions to
remain within specifications
10
Absolute resolution = 4.89 mV. At VREFHI = 5 V and VREFLO = 0 V, this s one LSB. As VREFHI decreases, VREFLO ncreases, or both, the LSB size
decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
ADC input pin circuit
One of the most common A/D application errors is inappropriate source impedance. In practice, minimum
source impedance should be used to limit the error as well as to minimize the required sampling time; however,
the source impedance must be smaller than Z
AI
. A typical ADC input pin circuit is shown in Figure 31.
VIN
R1
Requiv
VAI
(to ADCINx input)
R1 = 10
typical
Figure 31. Typical ADC Input Pin Circuit
A
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