參數(shù)資料
型號: TMS320C242PGA
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 7/66頁
文件大小: 803K
代理商: TMS320C242PGA
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’C242 PG and FN Packages (Continued)
NAME
64-PIN
QFP
NO.
68-PIN
PLCC
NO.
TYPE
RESET
STATE
DESCRIPTION
BIT I/O PINS
GPIO
IOPC2
45
56
I/O
IOPC3
IOPC4
IOPC5
IOPC6
IOPC7
46
57
I/O
GPIO
47
58
I/O
I
GPIO
48
59
I/O
GPIO
4
11
I/O
GPIO
3
10
I/O
GPIO
SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS
54
I/O
55
I/O
SCI asynchronous serial port receive data or GPIO
SCITXD/
IOPA0
SCIRXD/
IOPA1
43
SCI asynchronous serial port transmit data or GPIO
44
I
INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS
RS
27
35
I/O
I
Device reset. RS causes the ’C242 to terminate execution and sets
PC=0. After RS is brought to a high level, execution begins at location
zero of program memory. RS affects (sets to zero) various registers and
status bits. When the watchdog timer overflows, it initiates a system reset
pulse that is reflected on the RS pin. This pulse is eight clock cycles wide.
NMI§
53
64
I
I
Nonmaskable interrupt. When NMI is activated, the device is interrupted
regardless of the state of the INTM bit of the status register. NMI is
(falling) edge- and low-level-sensitive. To be recognized by the core, this
pin must be kept low for at least one clock cycle after the falling edge.
XINT1/
IOPA2
55
66
I/O
I
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-
sensitive. To be recognized by the core, these pins must be kept low/high
for at least one clock cycle after the edge. The edge polarity is
programmable.
XINT2/ADCSOC/
IOPD1
54
65
I/O
I
External user interrupt 2. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be
recognized by the core, these pins must be kept low/high for at least one
clock cycle after the edge. The edge polarity is programmable.
XF
/IOPC0§
39
50
I/O
O – 1
External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the
SETC XF/CLRC XF
instruction. This pin is configured as an external flag output by all device
resets. It can be used as a GPIO, if not used as XF.
BIO/
IOPC1§
42
53
I/O
I
Branch control input. BIO is polled by the
BCND pma,BIO
instruction. If
BIO is low, a branch is executed. If BIO is not used, it should be pulled
high. This pin is configured as a branch control input by all device resets.
It can be used as a GPIO, if not used as a branch control input.
PMT
49
60
I
I
Do not connect. Reserved for test.
CLOCK SIGNALS
XTAL1/CLKIN
35
46
I
I
PLL oscillator input pin. Crystal input to PLL/clock source input to
PLL. XTAL1/CLKIN is tied to one side of a reference crystal.
XTAL2
36
47
O
O
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a
reference crystal. This pin goes in the high-impedance state when
EMU1/OFF is active low.
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241).
NOTE:
Bold, italicized pin names
indicate pin function after reset.
A
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