參數(shù)資料
型號(hào)： TMS320C6205DZHK200
廠商： Texas Instruments
文件頁數(shù)： 24/73頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 288-BGA
標(biāo)準(zhǔn)包裝： 1
系列： TMS320C62x
類型： 定點(diǎn)
接口： McBSP，PCI
時(shí)鐘速率： 200MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.50V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 288-LFBGA
供應(yīng)商設(shè)備封裝： 288-BGA Microstar（16x16）
包裝： 托盤
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 1510)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 5.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
31
16
15
14
13
12
11
10
9
8
Reserved
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
PD3
PD2
PD1
R/W-0
7
0
Legend: R/Wx = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 8. PWRD Field of the CSR Register
Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the
CSR.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1
took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first,
then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE
bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute;
otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled
interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 5 summarizes all the power-down modes.
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