參數(shù)資料
型號: TMS320C6205DZHK200
廠商: Texas Instruments
文件頁數(shù): 38/73頁
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 288-BGA
標準包裝: 1
系列: TMS320C62x
類型: 定點
接口: McBSP,PCI
時鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 288-LFBGA
供應商設備封裝: 288-BGA Microstar(16x16)
包裝: 托盤
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-CKO2H)
Setup time, read EDx valid before CLKOUT2 high
1.25
ns
8
th(CKO2H-EDV)
Hold time, read EDx valid after CLKOUT2 high
3
ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles (see Figure 21Figure 26)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-CKO2H)
Output setup time, CEx valid before CLKOUT2 high
P 1
ns
2
toh(CKO2H-CEV)
Output hold time, CEx valid after CLKOUT2 high
P 3.5
ns
3
tosu(BEV-CKO2H)
Output setup time, BEx valid before CLKOUT2 high
P 1
ns
4
toh(CKO2H-BEIV)
Output hold time, BEx invalid after CLKOUT2 high
P 3.5
ns
5
tosu(EAV-CKO2H)
Output setup time, EAx valid before CLKOUT2 high
P 1
ns
6
toh(CKO2H-EAIV)
Output hold time, EAx invalid after CLKOUT2 high
P 3.5
ns
9
tosu(CASV-CKO2H)
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
P 1
ns
10
toh(CKO2H-CASV)
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
P 3.5
ns
11
tosu(EDV-CKO2H)
Output setup time, EDx valid before CLKOUT2 high§
P 3
ns
12
toh(CKO2H-EDIV)
Output hold time, EDx invalid after CLKOUT2 high
P 3.5
ns
13
tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE valid before CLKOUT2 high
P 1
ns
14
toh(CKO2H-WEV)
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P 3.5
ns
15
tosu(SDA10V-CKO2H)
Output setup time, SDA10 valid before CLKOUT2 high
P 1
ns
16
toh(CKO2H-SDA10IV)
Output hold time, SDA10 invalid after CLKOUT2 high
P 3.5
ns
17
tosu(RASV-CKO2H)
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
P 1
ns
18
toh(CKO2H-RASV)
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P 3.5
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
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