參數(shù)資料
型號(hào)： TMS320C6205DZHK200
廠商： Texas Instruments
文件頁(yè)數(shù)： 51/73頁(yè)
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 288-BGA
標(biāo)準(zhǔn)包裝： 1
系列： TMS320C62x
類型： 定點(diǎn)
接口： McBSP，PCI
時(shí)鐘速率： 200MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.50V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 288-LFBGA
供應(yīng)商設(shè)備封裝： 288-BGA Microstar（16x16）
包裝： 托盤
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
55
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP (see Figure 33)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
12
ns
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P2§
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C 2#
C + 2#
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
3
9
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int
1
4
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
CLKX ext
3
9
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
1
4
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
2
12
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid
FSX int
1
5
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX ext
2
12
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
# C = H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
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