參數(shù)資料
型號(hào): TMS320C6414TGLZ7
廠商: Texas Instruments
文件頁數(shù): 33/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED-POINT 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱: 296-17757
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
128
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY]
timing requirements for UXCLK (see Figure 57)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tc(UXCK)
Cycle time, UXCLK
20
ns
2
tw(UXCKH)
Pulse duration, UXCLK high
0.4tc(UXCK)
0.6tc(UXCK)
ns
3
tw(UXCKL)
Pulse duration, UXCLK low
0.4tc(UXCK)
0.6tc(UXCK)
ns
4
tt(UXCK)
Transition time, UXCLK
2
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
UXCLK
1
2
3
4
Figure 57. UXCLK Timing
timing requirements for URCLK (see Figure 58)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tc(URCK)
Cycle time, URCLK
20
ns
2
tw(URCKH)
Pulse duration, URCLK high
0.4tc(URCK)
0.6tc(URCK)
ns
3
tw(URCKL)
Pulse duration, URCLK low
0.4tc(URCK)
0.6tc(URCK)
ns
4
tt(URCK)
Transition time, URCLK
2
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
URCLK
1
2
3
4
Figure 58. URCLK Timing
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