參數(shù)資料
型號： TMS320C6414TGLZ7
廠商： Texas Instruments
文件頁數(shù)： 85/146頁
文件大?。?/td> 0K
描述： IC DSP FIXED-POINT 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 720MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱： 296-17757
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
I
Device reset
NMI
B4
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it
is recommended that the NMI pin be grounded versus relying on the IPD.
GP7/EXT_INT7
AF4
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
default after reset setting is GPIO enabled as input-only.
GP6/EXT_INT6
AD5
I/O/Z
IPU
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding interrupt
GP5/EXT_INT5
AE5
I/O/Z
IPU
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
GP4/EXT_INT4
AF5
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
GP15/PRST§
G3
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GP14/PCLK§
F2
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
GP13/PINTA§
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GP12/PGNT§
J3
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GP11/PREQ§
F1
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GP10/PCBE3§
L2
I/O/Z
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GP9/PIDSEL§
M3
I/O/Z
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
GP3
AC6
IPD
GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only.
GP0
AF6
IPD
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)
[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)
signal (output only).
CLKS2/GP8§
AE4
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro-
grammed as a GPIO 8 pin (I/O/Z).
CLKOUT6/GP2§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
CLKOUT4/GP1§
AE6
I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only]
PCI_EN
AA4
I
IPD
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals. This pin works in conjunction with the MCBSP2_EN pin to enable/disable
other peripherals (for more details, see the Device Configurations section of this data sheet).
HINT/PFRAME§
R4
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
HCNTL1/
PDEVSEL§
R1
I/O/Z
Host control selects between control, address, or data registers (I) [default] or PCI device
select (I/O/Z).
HCNTL0/
PSTOP§
T4
I/O/Z
Host control selects between control, address, or data registers (I) [default] or PCI stop
(I/O/Z)
HHWIL/PTRDY§
R3
I/O/Z
Host half-word select first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
HR/W/PCBE2§
P1
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
For the C6414T device, only these pins are multiplexed pins.
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