參數(shù)資料
型號(hào)： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 13/116頁(yè)
文件大?。?/td> 999K
代理商： TMS320C6727B_07
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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
The five bus masters arbitrate for five different target groups:
T1
T2
T3
T4
T5
On-chip memories through the CPU Slave Port (CSP).
Memories on the external memory interface (EMIF).
Peripheral registers through the peripheral configuration bus.
McASP serializers through the dedicated McASP DMA bus.
dMAX registers.
The crossbar switch supports parallel accesses from different bus masters to different targets. When two
or more bus masters contend for the same target beginning at the same cycle, then the highest-priority
master is given ownership of the target while the other master(s) are stalled. However, once ownership of
the target is given to a bus master, it is allowed to complete its access before ownership is arbitrated
again. Following are two examples.
Example 1:
Simultaneous accesses without conflict
dMAX HiMAX accesses McASP Data Port for transfer of audio data.
dMAX LoMAX accesses SPI port for control processing.
UHPI accesses internal RAM through the CSP.
CPU fills program cache from EMIF.
Example 2:
Conflict over a shared resource
dMAX HiMAX accesses RTI port for McASP sample rate measurement.
dMAX LoMAX accesses SPI port for control processing.
In Example 2, both masters contend for the same target, the peripheral configuration bus. The HiMAX
access will be given priority over the LoMAX access.
The master priority is illustrated in
Figure 2-4
by the numbers 1 through 4 in the bus arbiter symbols. Note
that the EMIF arbitration is distributed so that only one bridge crossing is necessary for PMP accesses.
The effect is that PMP has 5th priority to the EMIF but lower latency.
A bus bridge is needed between masters and targets which run at different clock rates. The bus bridge
contains a small FIFO to allow the bridge to accept an incoming (burst) access at one clock rate and pass
it through the bridge to a target running at a different rate.
Table 2-6
lists the FIFO properties of the four
bridges (BR1, BR2, BR3, and BR4) in
Figure 2-4
.
Table 2-6. Bus Bridges
LABEL
BR1
BR2
BR3
BR4
BRIDGE DESCRIPTION
MASTER CLOCK
SYSCLK1
SYSCLK2
SYSCLK1
SYSCLK2
TARGET CLOCK
SYSCLK2
SYSCLK1
SYSCLK3
SYSCLK3
DMP Bridge to peripherals, dMAX, EMIF
dMAX, UHPI to ROM/RAM (CSP)
PMP to EMIF
CPU, UHPI, and dMAX to EMIF
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Device Overview
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