參數(shù)資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 42/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
Table 4-2
lists how the synchronization events are associated with event numbers in the dMAX controller.
Table 4-2. dMAX Peripheral Event Input Assignments
EVENT NUMBER
0
EVENT ACRONYM
DETR[0]
EVENT DESCRIPTION
The CPU triggers the event by creating appropriate transition (edge) on bit0
in DETR register.
The CPU triggers the event by creating appropriate transition (edge) on bit16
in DETR register.
RTI DMA REQ[0]
RTI DMA REQ[1]
McASP0 TX DMA REQ
McASP0 RX DMA REQ
McASP1 TX DMA REQ
McASP1 RX DMA REQ
McASP2 TX DMA REQ
McASP2 RX DMA REQ
The CPU triggers the event by creating appropriate transition (edge) on bit1
in DETR register.
The CPU triggers the event by creating appropriate transition (edge) on bit17
in DETR register.
UHPI CPU_INT
SPI0 DMA_RX_REQ
SPI1 DMA_RX_REQ
RTI DMA REQ[2]
RTI DMA REQ[3]
The CPU triggers the event by creating appropriate transition (edge) on bit2
in DETR register.
The CPU triggers the event by creating appropriate transition (edge) on bit18
in DETR register.
I2C 0 Transmit Event
I2C 0 Receive Event
I2C 1 Transmit Event
I2C 1 Receive Event
The CPU triggers the event by creating appropriate transition (edge) on bit3
in DETR register.
The CPU triggers the event by creating appropriate transition (edge) on bit19
in DETR register.
1
DETR[16]
2
3
4
5
6
7
8
9
10
RTIREQ0
RTIREQ1
MCASP0TX
MCASP0RX
MCASP1TX
MCASP1RX
MCASP2TX
MCASP2RX
DETR[1]
11
DETR[17]
12
13
14
15
16
17
UHPIINT
SPI0RX
SPI1RX
RTIREQ2
RTIREQ3
DETR[2]
18
DETR[18]
19
20
21
22
23
I2C0XEVT
I2C0REVT
I2C1XEVT
I2C1REVT
DETR[3]
24
DETR[19]
25
26
27
28
29
30
Reserved
MCASP0ERR
MCASP1ERR
MCASP2ERR
OVLREQ[0/1]
DETR[20]
AMUTEIN0 or McASP0 TX INT or McASP0 RX INT (error on McASP0)
AMUTEIN1 or McASP1 TX INT or McASP1 RX INT (error on McASP1)
AMUTEIN2 or McASP2 TX INT or McASP2 RX INT (error on McASP2)
Error on RTI
The CPU triggers the event by creating appropriate transition (edge) on bit20
in DETR register.
The CPU triggers the event by creating appropriate transition (edge) on bit21
in DETR register.
31
DETR[21]
Peripheral and Electrical Specifications
42
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