參數(shù)資料
型號(hào)： TMS320UVC5409
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor(定點(diǎn)DSP)
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的
文件頁(yè)數(shù)： 18/35頁(yè)
文件大小： 443K
代理商： TMS320UVC5409
TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial ports (continued)
The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family
of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX
pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register
(DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure
allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on
the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR
is available. This structure allows storage of the two previous words while the reception of the current word is
in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial port functions, the McBSP provides programmable clock and frame sync
generation. Among the programmable functions are:
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame sync polarity
The on-chip companding hardware allows compression and expansion of data in either
μ
-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received data
is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,
multichannel selection allows independent enabling of particular channels for transmission and reception. Up
to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is
configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a
slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
hardware timer
The ’UVC5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer
is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.
A
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